
#ifdef TSINGMA_MX

#include "usw/include/drv_common.h"
#include "usw/include/drv_enum.h"
#include "usw/include/drv_ftm.h"
#include "usw/include/drv_ser.h"

#undef DRV_DEF_C
#undef DRV_DEF_M
#undef DRV_DEF_D
#undef DRV_DEF_F
#undef DRV_DEF_E

#ifdef DRV_DEF_C
	#error DRV_DEF_C has been defined
#endif

#ifdef DRV_DEF_M
	#error DRV_DEF_M has been defined
#endif

#ifdef DRV_DEF_D
	#error DRV_DEF_D has been defined
#endif

#ifdef DRV_DEF_F
	#error DRV_DEF_F has been defined
#endif

#ifdef DRV_DEF_E
	#error DRV_DEF_E has been defined
#endif

#define DRV_DEF_DD(ModuleName, InstNum, RegName,RegName2,SliceType, OpType, Entry, Word, EntryOffset, ...)
#define DRV_DEF_FF(ModuleName, InstNum, RegName, RegName2, ...)

extern tables_info_t drv_tmm_tbls_list[];

#if(SDK_WORK_PLATFORM == 1)
 /*DS ADDR*/
#define CTC_DS_ADDR(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, SdbType, SdbRead, TcamMem, Bus, Stats, ...) \
   static addrs_t RegName##_tbl_addrs_tmm[(0==InstNum)?(2):(InstNum*2)] = {__VA_ARGS__, 0x80000000};
#else
#define CTC_DS_ADDR(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, SdbType, SdbRead, TcamMem, Bus, Stats, ...) \
   static addrs_t RegName##_tbl_addrs_tmm[(0==InstNum)?(1):(InstNum)] = {__VA_ARGS__};
#endif

#if(SDK_WORK_PLATFORM == 1)
 /*DS LIST*/
#define CTC_DS_INFO(ModuleName, RegName, RegAlias, SliceType, OpType, Entry, Word, EntryOffset, SdbType, SdbRead, TcamMem, Bus, Stats, ...) \
   { \
      SliceType, \
      OpType, \
      Entry * ((sizeof(RegName##_tbl_addrs_tmm)/sizeof(addrs_t)) / 2), \
      0, \
      Word*4, \
      SdbType, \
      SdbRead, \
      Bus,    \
      Stats,  \
      sizeof(RegName##_tbl_addrs_tmm)/sizeof(addrs_t), \
      0,\
      sizeof(RegAlias##_tbl_fields_tmm)/sizeof(fields_t), \
      EntryOffset*4, \
      TcamMem,  \
      DRV_FEATURE_MODE_PER_CORE, \
      RegName##_t,\
      0, \
      RegName##_tbl_addrs_tmm, \
      RegAlias##_tbl_fields_tmm, \
   },

  #define CTC_DS_INFO1(ModuleName, RegName, RegAlias, SliceType, OpType, Entry, Word, EntryOffset, SdbType, SdbRead, TcamMem, Bus, Stats, ...) \
   { \
      #ModuleName, \
      #RegName, \
      RegAlias##_tbl_fields_name_tmm, \
   },
#else
    /*DS LIST*/
#define CTC_DS_INFO(ModuleName, RegName, RegAlias, SliceType, OpType, Entry, Word, EntryOffset, SdbType, SdbRead, TcamMem, Bus, Stats, ...) \
   { \
      SliceType, \
      OpType, \
      Entry * (sizeof(RegName##_tbl_addrs_tmm)/sizeof(addrs_t)), \
      0, \
      Word*4, \
      SdbType,\
      SdbRead, \
      Bus,    \
      Stats,  \
      sizeof(RegName##_tbl_addrs_tmm)/sizeof(addrs_t), \
      0,\
      sizeof(RegAlias##_tbl_fields_tmm)/sizeof(fields_t), \
      EntryOffset*4, \
      TcamMem, \
      DRV_FEATURE_MODE_PER_CORE, \
      RegName##_t,\
      0, \
      RegName##_tbl_addrs_tmm, \
      RegAlias##_tbl_fields_tmm, \
   },

#define CTC_DS_INFO1(ModuleName, RegName, RegAlias, SliceType, OpType, Entry, Word, EntryOffset, SdbType, SdbRead, TcamMem, Bus, Stats, ...) \
   { \
      #ModuleName, \
      #RegName, \
      RegAlias##_tbl_fields_name_tmm, \
   },
#endif

#define CTC_FIELD_E_INFO() \
   { \
   0, \
   0, \
   0, \
   NULL, \
   },
#define CTC_FIELD_E_INFO1() \
    { \
    "Invalid", \
    },


 /*Field Addr*/
#define CTC_FIELD_ADDR(ModuleName, RegName, FieldName, FullName, Bits, ...) \
  static segs_t RegName##_##FieldName##_tbl_segs_tmm[] = {__VA_ARGS__};

 /*Field Info*/
#define CTC_FIELD_INFO(ModuleName, RegName, FieldName, FullName, Bits, ...) \
   { \
      RegName##_##FieldName##_f,\
      Bits, \
      sizeof(RegName##_##FieldName##_tbl_segs_tmm) / sizeof(segs_t), \
      RegName##_##FieldName##_tbl_segs_tmm, \
   },

#define CTC_FIELD_INFO1(ModuleName, RegName, FieldName, FullName, Bits, ...) \
    { \
      #FullName, \
    },

 /*DS Field List Seperator*/
#define CTC_DS_SEPERATOR_INFO(ModuleName, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...) \
 }; \
 static fields_t RegName##_tbl_fields_tmm[] = {


#define DRV_DEF_C(MaxInstNum, MaxEntry, MaxWord, EntryOffset, MaxBits,MaxStartPos,MaxSegSize)

 /* Segment Info*/
#define DRV_DEF_M(ModuleName, InstNum)
#ifdef DRV_DS_LITE
#define DRV_DEF_D(RegName, Word, No)
#define DRV_DEF_F(RegName, FieldName, No)
#else
#define DRV_DEF_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...)
#define DRV_DEF_F(ModuleName, InstNum, RegName, FieldName, FullName, Bits, ...) \
        CTC_FIELD_ADDR(ModuleName, RegName, FieldName, FullName, Bits, __VA_ARGS__)
#endif
#define DRV_DEF_SDK_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...)
#define DRV_DEF_SDK_F(ModuleName, InstNum, RegName, FieldName, FullName,Bits, ...) \
        CTC_FIELD_ADDR(ModuleName, RegName, FieldName, FullName, Bits, __VA_ARGS__)
#define DRV_DEF_E()
#define DRV_DEF_FIELD_E()
#include "usw/include/drv_ds_tmm.h"
#undef DRV_DEF_M
#undef DRV_DEF_D
#undef DRV_DEF_F
#undef DRV_DEF_E
#undef DRV_DEF_SDK_D
#undef DRV_DEF_SDK_F
#undef DRV_DEF_FIELD_E

 /* Field Info*/
#define DRV_DEF_M(ModuleName, InstNum)
#ifdef DRV_DS_LITE
#define DRV_DEF_D(RegName, Word, No)
#define DRV_DEF_F(RegName, FieldName, No)
#else
#define DRV_DEF_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...) \
        CTC_DS_SEPERATOR_INFO(ModuleName, RegName, SliceType, OpType, Entry, Word, EntryOffset, __VA_ARGS__)
#define DRV_DEF_F(ModuleName, InstNum, RegName, FieldName, FullName, Bits, ...) \
        CTC_FIELD_INFO(ModuleName, RegName, FieldName, FullName, Bits, __VA_ARGS__)
#endif
#define DRV_DEF_SDK_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...) \
        CTC_DS_SEPERATOR_INFO(ModuleName, RegName, SliceType, OpType, Entry, Word, EntryOffset, __VA_ARGS__)
#define DRV_DEF_SDK_F(ModuleName, InstNum, RegName, FieldName,FullName, Bits, ...) \
        CTC_FIELD_INFO(ModuleName, RegName, FieldName, FullName, Bits, __VA_ARGS__)
#define DRV_DEF_E()
#define DRV_DEF_FIELD_E() CTC_FIELD_E_INFO()

fields_t tmm_fields_1st = {0,0,0,NULL
#include "usw/include/drv_ds_tmm.h"
};

#ifndef DRV_DS_LITE
#undef DRV_DEF_M
#undef DRV_DEF_D
#undef DRV_DEF_F
#undef DRV_DEF_DD
#undef DRV_DEF_E
#undef DRV_DEF_SDK_D
#undef DRV_DEF_SDK_F
#undef DRV_DEF_FIELD_E
#undef CTC_DS_SEPERATOR_INFO

#define CTC_DS_SEPERATOR_INFO(ModuleName, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...) \
 }; \
 static fields_name_t RegName##_tbl_fields_name_tmm[] = {

  /* Field Name Info*/
#define DRV_DEF_M(ModuleName, InstNum)
#ifdef DRV_DS_LITE
#define DRV_DEF_D(RegName, Word, No)
#define DRV_DEF_F(RegName, FieldName, No)
#else
#define DRV_DEF_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...) \
         CTC_DS_SEPERATOR_INFO(ModuleName, RegName, SliceType, OpType, Entry, Word, EntryOffset, __VA_ARGS__)
#define DRV_DEF_F(ModuleName, InstNum, RegName, FieldName, FullName, Bits, ...) \
         CTC_FIELD_INFO1(ModuleName, RegName, FieldName, FullName, Bits, __VA_ARGS__)
#endif
#define DRV_DEF_SDK_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...) \
         CTC_DS_SEPERATOR_INFO(ModuleName, RegName, SliceType, OpType, Entry, Word, EntryOffset, __VA_ARGS__)
#define DRV_DEF_SDK_F(ModuleName, InstNum, RegName, FieldName,FullName, Bits, ...) \
         CTC_FIELD_INFO1(ModuleName, RegName, FieldName, FullName, Bits, __VA_ARGS__)
#define DRV_DEF_E()
#define DRV_DEF_FIELD_E() CTC_FIELD_E_INFO1()
 
 fields_name_t tmm_fields_name = {NULL
#include "usw/include/drv_ds_tmm.h"
 };
#endif

#undef DRV_DEF_M
#undef DRV_DEF_D
#undef DRV_DEF_F
#undef DRV_DEF_DD
#undef DRV_DEF_E
#undef DRV_DEF_SDK_D
#undef DRV_DEF_SDK_F
#undef DRV_DEF_FIELD_E

 /* DS Address*/
#define DRV_DEF_M(ModuleName, InstNum)
#ifdef DRV_DS_LITE
#define DRV_DEF_D(RegName, Word, No)
#define DRV_DEF_F(RegName, FieldName, No)
#else
#define DRV_DEF_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...) \
        CTC_DS_ADDR(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, __VA_ARGS__)
#define DRV_DEF_F(ModuleName, InstNum, RegName, FieldName, FullName, Bits, ...)
#endif
#define DRV_DEF_DD(ModuleName, InstNum, RegName, RegAlias, SliceType, OpType, Entry, Word, EntryOffset, ...) \
        CTC_DS_ADDR(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, __VA_ARGS__)
#define DRV_DEF_E()
#define DRV_DEF_FIELD_E()
#define DRV_DEF_SDK_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...) \
        CTC_DS_ADDR(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, __VA_ARGS__)
#define DRV_DEF_SDK_F(ModuleName, InstNum, RegName, FieldName, FullName, Bits, ...)
#include "usw/include/drv_ds_tmm.h"
#undef DRV_DEF_M
#undef DRV_DEF_D
#undef DRV_DEF_F
#undef DRV_DEF_E
#undef DRV_DEF_SDK_D
#undef DRV_DEF_SDK_F

#undef DRV_DEF_DD
#undef DRV_DEF_FIELD_E

 /* DS List*/
#define DRV_DEF_M(ModuleName, InstNum)
#ifdef DRV_DS_LITE
#define DRV_DEF_D(RegName, Word, No)
#define DRV_DEF_F(RegName, FieldName, No)
#else
#define DRV_DEF_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...) \
        CTC_DS_INFO(ModuleName, RegName, RegName, SliceType, OpType, Entry, Word, EntryOffset, __VA_ARGS__)
#define DRV_DEF_F(ModuleName, InstNum, RegName, FieldName, FullName, Bits, ...)
#endif
#define DRV_DEF_DD(ModuleName, InstNum, RegName, RegAlias,SliceType, OpType, Entry, Word, EntryOffset, ...) \
        CTC_DS_INFO(ModuleName, RegName, RegAlias, SliceType, OpType, Entry, Word, EntryOffset, __VA_ARGS__)
#define DRV_DEF_SDK_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...) \
        CTC_DS_INFO(ModuleName, RegName, RegName, SliceType, OpType, Entry, Word, EntryOffset, __VA_ARGS__)
#define DRV_DEF_SDK_F(ModuleName, InstNum, RegName, FieldName, Bits, ...)
#define DRV_DEF_E()
#define DRV_DEF_FIELD_E()

tables_info_t drv_tmm_tbls_list[] = {
#include "usw/include/drv_ds_tmm.h"
{0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,NULL,NULL}
};
#ifndef DRV_DS_LITE
#undef DRV_DEF_M
#undef DRV_DEF_D
#undef DRV_DEF_F
#undef DRV_DEF_E
#undef DRV_DEF_SDK_D
#undef DRV_DEF_SDK_F
        
#undef DRV_DEF_DD
#undef DRV_DEF_FIELD_E

     /* DS List name*/
#define DRV_DEF_M(ModuleName, InstNum)
#ifdef DRV_DS_LITE
#define DRV_DEF_D(RegName, Word, No)
#define DRV_DEF_F(RegName, FieldName, No)
#else
#define DRV_DEF_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...) \
                CTC_DS_INFO1(ModuleName, RegName, RegName, SliceType, OpType, Entry, Word, EntryOffset, __VA_ARGS__)
#define DRV_DEF_F(ModuleName, InstNum, RegName, FieldName, FullName, Bits, ...)
#endif
#define DRV_DEF_DD(ModuleName, InstNum, RegName, RegAlias,SliceType, OpType, Entry, Word, EntryOffset, ...) \
                CTC_DS_INFO1(ModuleName, RegName, RegAlias, SliceType, OpType, Entry, Word, EntryOffset, __VA_ARGS__)
#define DRV_DEF_SDK_D(ModuleName, InstNum, RegName, SliceType, OpType, Entry, Word, EntryOffset, ...) \
                CTC_DS_INFO1(ModuleName, RegName, RegName, SliceType, OpType, Entry, Word, EntryOffset, __VA_ARGS__)
#define DRV_DEF_SDK_F(ModuleName, InstNum, RegName, FieldName, Bits, ...)
#define DRV_DEF_E()
#define DRV_DEF_FIELD_E()


tables_name_t drv_tmm_tbls_name_list[] = {
#include "usw/include/drv_ds_tmm.h"
{NULL, NULL, NULL}
};
#endif

/*ECC Interrupt*/
#define DRV_ECC_F(...)    {__VA_ARGS__},

uint32 drv_tmm_enum[DRV_CONSTANT_MAX];
drv_mem_t drv_tmm_mem[DRV_FTM_MAX_ID];
uint32 drv_tmm_tcam_mem_map[] =
{
    UserIdHashTcamMem_t,         /*0*/
    UserIdTcamMem_t,             /*1*/
    ProgramAclTcamMem_t,         /*2*/
    EgressAclTcamTcamMem_t,      /*3*/
    EgrSclHashTcamMem_t,         /*4*/
    LpmTcamTcamMem_t,            /*5*/
    IpeCidTcamMem_t,             /*6*/
    DsLtidSelectTcamMem_t,       /*7*/
    IpeHdrAdjRouterMacTcamMem_t, /*8*/
    IpeHdrAdjUdfTcamMem_t,       /*9*/
    DsUserIdHash0TcamAdMem_t,    /*10*/
    DsUserIdHash1TcamAdMem_t,    /*11*/
    DsUserIdTcam0AdMem_t,        /*12*/
    DsUserIdTcam1AdMem_t,        /*13*/
    DsAclIngress_t,              /*14*/
    DsAclEgress_t,               /*15*/
    DsEgressScl0TcamAd_t,        /*16*/
    DsEgressScl1TcamAd_t,        /*17*/
    LpmTcamAdMem_t               /*18*/
};

drv_ecc_intr_tbl_t drv_ecc_tmm_err_intr_tbl[] =
{
#include "usw/include/drv_ecc_intr_tmm.h"
    {MaxTblId_t,0,0,0,0,0,0,0,0}
};

drv_ecc_sbe_cnt_t drv_ecc_tmm_sbe_cnt[] =
{
    {MaxTblId_t,BufRetrvDPParityStatus_t,BufRetrvDPParityStatus_bufRetrvBufInfoMemSbeCnt_f},
    {BufRetrvEpeRam0_t,BufRetrvDPParityStatus_t,BufRetrvDPParityStatus_bufRetrvEpeRam0SbeCnt_f},
    {BufRetrvEpeRam1_t,BufRetrvDPParityStatus_t,BufRetrvDPParityStatus_bufRetrvEpeRam1SbeCnt_f},
    {BufRetrvEpeRam2_t,BufRetrvDPParityStatus_t,BufRetrvDPParityStatus_bufRetrvEpeRam2SbeCnt_f},
    {BufRetrvEpeRam3_t,BufRetrvDPParityStatus_t,BufRetrvDPParityStatus_bufRetrvEpeRam3SbeCnt_f},
    {BufRetrvEpeRam4_t,BufRetrvDPParityStatus_t,BufRetrvDPParityStatus_bufRetrvEpeRam4SbeCnt_f},
    {BufRetrvMsgParkMem_t,BufRetrvDPParityStatus_t,BufRetrvDPParityStatus_bufRetrvMsgParkMemSbeCnt_f},
    {BufRetrvPktMsgMem_t,BufRetrvDPParityStatus_t,BufRetrvDPParityStatus_bufRetrvPktMsgMemSbeCnt_f},
    {MaxTblId_t,BufRetrvDPParityStatus_t,BufRetrvDPParityStatus_bufRetrvRam0SelFifoSbeCnt_f},
    {MaxTblId_t,BufRetrvDPParityStatus_t,BufRetrvDPParityStatus_bufRetrvRam1SelFifoSbeCnt_f},
    {MaxTblId_t,BufRetrvDPParityStatus_t,BufRetrvDPParityStatus_bufRetrvRam2SelFifoSbeCnt_f},
    {MaxTblId_t,BufRetrvDPParityStatus_t,BufRetrvDPParityStatus_bufRetrvRam3SelFifoSbeCnt_f},
    {MaxTblId_t,BufRetrvDPParityStatus_t,BufRetrvDPParityStatus_bufRetrvRam4SelFifoSbeCnt_f},
    {MaxTblId_t,BufRetrvDPParityStatus_t,BufRetrvDPParityStatus_bufRetrvRam5SelFifoSbeCnt_f},
    {MaxTblId_t,BufRetrvDPParityStatus_t,BufRetrvDPParityStatus_bufRetrvRam6SelFifoSbeCnt_f},
    {MaxTblId_t,BufRetrvDPParityStatus_t,BufRetrvDPParityStatus_bufRetrvRam7SelFifoSbeCnt_f},
    {MaxTblId_t,BufRetrvDPParityStatus_t,BufRetrvDPParityStatus_bufRetrvBufInfoMemSbeCnt_f, 1},
    {BufRetrvEpeRam0_t,BufRetrvDPParityStatus_t,BufRetrvDPParityStatus_bufRetrvEpeRam0SbeCnt_f, 1},
    {BufRetrvEpeRam1_t,BufRetrvDPParityStatus_t,BufRetrvDPParityStatus_bufRetrvEpeRam1SbeCnt_f, 1},
    {BufRetrvEpeRam2_t,BufRetrvDPParityStatus_t,BufRetrvDPParityStatus_bufRetrvEpeRam2SbeCnt_f, 1},
    {BufRetrvEpeRam3_t,BufRetrvDPParityStatus_t,BufRetrvDPParityStatus_bufRetrvEpeRam3SbeCnt_f, 1},
    {BufRetrvEpeRam4_t,BufRetrvDPParityStatus_t,BufRetrvDPParityStatus_bufRetrvEpeRam4SbeCnt_f, 1},
    {BufRetrvMsgParkMem_t,BufRetrvDPParityStatus_t,BufRetrvDPParityStatus_bufRetrvMsgParkMemSbeCnt_f, 1},
    {BufRetrvPktMsgMem_t,BufRetrvDPParityStatus_t,BufRetrvDPParityStatus_bufRetrvPktMsgMemSbeCnt_f, 1},
    {MaxTblId_t,BufRetrvDPParityStatus_t,BufRetrvDPParityStatus_bufRetrvRam0SelFifoSbeCnt_f, 1},
    {MaxTblId_t,BufRetrvDPParityStatus_t,BufRetrvDPParityStatus_bufRetrvRam1SelFifoSbeCnt_f, 1},
    {MaxTblId_t,BufRetrvDPParityStatus_t,BufRetrvDPParityStatus_bufRetrvRam2SelFifoSbeCnt_f, 1},
    {MaxTblId_t,BufRetrvDPParityStatus_t,BufRetrvDPParityStatus_bufRetrvRam3SelFifoSbeCnt_f, 1},
    {MaxTblId_t,BufRetrvDPParityStatus_t,BufRetrvDPParityStatus_bufRetrvRam4SelFifoSbeCnt_f, 1},
    {MaxTblId_t,BufRetrvDPParityStatus_t,BufRetrvDPParityStatus_bufRetrvRam5SelFifoSbeCnt_f, 1},
    {MaxTblId_t,BufRetrvDPParityStatus_t,BufRetrvDPParityStatus_bufRetrvRam6SelFifoSbeCnt_f, 1},
    {MaxTblId_t,BufRetrvDPParityStatus_t,BufRetrvDPParityStatus_bufRetrvRam7SelFifoSbeCnt_f, 1},
    {BufRetrvLinkList0Ram_t,BufRetrvShareParityStatus_t,BufRetrvShareParityStatus_bufRetrvLinkList0RamSbeCnt_f},
    {BsWalkLinkListRtnFifo_t,BufStoreDpCtlParityStatus_t,BufStoreDpCtlParityStatus_bsWalkLinkListRtnFifoSbeCnt_f},
    {BsWalkLinkListRtnFifo_t,BufStoreDpCtlParityStatus_t,BufStoreDpCtlParityStatus_bsWalkLinkListRtnFifoSbeCnt_f, 1},
    {MaxTblId_t,BufStoreProcParityStatus_t,BufStoreProcParityStatus_bsBrSlice0Dp0CellSbeCnt_f},
    {MaxTblId_t,BufStoreProcParityStatus_t,BufStoreProcParityStatus_bsBrSlice0Dp1CellSbeCnt_f},
    {MaxTblId_t,BufStoreProcParityStatus_t,BufStoreProcParityStatus_bsIpeFreePtrFifoSlice0Dp0SbeCnt_f},
    {MaxTblId_t,BufStoreProcParityStatus_t,BufStoreProcParityStatus_bsIpeFreePtrFifoSlice0Dp1SbeCnt_f},
    {BsMetFifoReleaseFifo0_t,BufStoreProcParityStatus_t,BufStoreProcParityStatus_bsMetFifoReleaseFifo0SbeCnt_f},
    {BsPktAbortReqFifo0_t,BufStoreProcParityStatus_t,BufStoreProcParityStatus_bsPktAbortReqFifo0SbeCnt_f},
    {BsPktAbortReqFifo1_t,BufStoreProcParityStatus_t,BufStoreProcParityStatus_bsPktAbortReqFifo1SbeCnt_f},
    {MaxTblId_t,BufStoreProcParityStatus_t,BufStoreProcParityStatus_bsWrCtlMsgLinkListFifo0SbeCnt_f},
    {MaxTblId_t,BufStoreProcParityStatus_t,BufStoreProcParityStatus_bsWrCtlMsgLinkListFifo1SbeCnt_f},
    {BufStoreFreeListRam0_t,BufStoreProcParityStatus_t,BufStoreProcParityStatus_bufStoreFreeListRam0SbeCnt_f},
    {BufStoreFreeListRam1_t,BufStoreProcParityStatus_t,BufStoreProcParityStatus_bufStoreFreeListRam1SbeCnt_f},
    {BufStoreFreeListRam2_t,BufStoreProcParityStatus_t,BufStoreProcParityStatus_bufStoreFreeListRam2SbeCnt_f},
    {BufStoreFreeListRam3_t,BufStoreProcParityStatus_t,BufStoreProcParityStatus_bufStoreFreeListRam3SbeCnt_f},
    {BufStoreFreeListRam4_t,BufStoreProcParityStatus_t,BufStoreProcParityStatus_bufStoreFreeListRam4SbeCnt_f},
    {BufStoreFreeListRam5_t,BufStoreProcParityStatus_t,BufStoreProcParityStatus_bufStoreFreeListRam5SbeCnt_f},
    {BufStoreFreeListRam6_t,BufStoreProcParityStatus_t,BufStoreProcParityStatus_bufStoreFreeListRam6SbeCnt_f},
    {BufStoreFreeListRam7_t,BufStoreProcParityStatus_t,BufStoreProcParityStatus_bufStoreFreeListRam7SbeCnt_f},
    {EncapMem_t,CpuMapParityStatus_t,CpuMapParityStatus_encapMemSbeCnt_f},
    {EncapPktDataMem_t,CpuMapParityStatus_t,CpuMapParityStatus_encapPktDataMemSbeCnt_f},
    {DmaDescCache_t,DmaCtlParityStatus_t,DmaCtlParityStatus_dmaDescCacheSbeCnt_f},
    {DmaInfoMem_t,DmaCtlParityStatus_t,DmaCtlParityStatus_dmaInfoMemSbeCnt_f},
    {DmaPktRxMem_t,DmaCtlParityStatus_t,DmaCtlParityStatus_dmaPktRxMemSbeCnt_f},
    {DmaPktTxMem_t,DmaCtlParityStatus_t,DmaCtlParityStatus_dmaPktTxMemSbeCnt_f},
    {DmaRegRdMem_t,DmaCtlParityStatus_t,DmaCtlParityStatus_dmaRegRdMemSbeCnt_f},
    {DmaScanWrMem_t,DmaCtlParityStatus_t,DmaCtlParityStatus_dmaScanWrMemSbeCnt_f},
    {DmaUserRegMem_t,DmaCtlParityStatus_t,DmaCtlParityStatus_dmaUserRegMemSbeCnt_f},
    {DmaWrReqDataFifo_t,DmaCtlParityStatus_t,DmaCtlParityStatus_dmaWrReqDataFifoSbeCnt_f},
    {DsAgingStatusFib_t,DsAgingParityStatus_t,DsAgingParityStatus_dsAgingStatusFibSbeCnt_f},
    {DsAgingStatusTcam_t,DsAgingParityStatus_t,DsAgingParityStatus_dsAgingStatusTcamSbeCnt_f},
    {DsAging_t,DsAgingParityStatus_t,DsAgingParityStatus_dsAgingSbeCnt_f},
    {MaxTblId_t,DynamicAdParityStatus_t,DynamicAdParityStatus_shareAdRam0SbeCnt_f},
    {MaxTblId_t,DynamicAdParityStatus_t,DynamicAdParityStatus_shareAdRam1SbeCnt_f},
    {MaxTblId_t,DynamicAdParityStatus_t,DynamicAdParityStatus_shareAdRam2SbeCnt_f},
    {MaxTblId_t,DynamicAdParityStatus_t,DynamicAdParityStatus_shareAdRam3SbeCnt_f},
    {MaxTblId_t,DynamicAdParityStatus_t,DynamicAdParityStatus_shareAdRam4SbeCnt_f},
    {MaxTblId_t,DynamicAdParityStatus_t,DynamicAdParityStatus_shareAdRam5SbeCnt_f},
    {MaxTblId_t,DynamicAdParityStatus_t,DynamicAdParityStatus_shareAdRam6SbeCnt_f},
    {MaxTblId_t,DynamicEditParityStatus_t,DynamicEditParityStatus_shareEditRam0SbeCnt_f},
    {MaxTblId_t,DynamicEditParityStatus_t,DynamicEditParityStatus_shareEditRam1SbeCnt_f},
    {MaxTblId_t,DynamicEditParityStatus_t,DynamicEditParityStatus_shareEditRam2SbeCnt_f},
    {MaxTblId_t,DynamicEditParityStatus_t,DynamicEditParityStatus_shareEditRam3SbeCnt_f},
    {MaxTblId_t,DynamicEditParityStatus_t,DynamicEditParityStatus_shareEditRam4SbeCnt_f},
    {MaxTblId_t,DynamicEditParityStatus_t,DynamicEditParityStatus_shareEditRam5SbeCnt_f},
    {MaxTblId_t,DynamicFibKeyParityStatus_t,DynamicFibKeyParityStatus_shareKeyRam0SbeCnt_f},
    {MaxTblId_t,DynamicFibKeyParityStatus_t,DynamicFibKeyParityStatus_shareKeyRam1SbeCnt_f},
    {MaxTblId_t,DynamicFibKeyParityStatus_t,DynamicFibKeyParityStatus_shareKeyRam2SbeCnt_f},
    {MaxTblId_t,DynamicFibKeyParityStatus_t,DynamicFibKeyParityStatus_shareKeyRam3SbeCnt_f},
    {MaxTblId_t,DynamicFibKeyParityStatus_t,DynamicFibKeyParityStatus_shareKeyRam4SbeCnt_f},
    {MaxTblId_t,DynamicFibKeyParityStatus_t,DynamicFibKeyParityStatus_shareKeyRam5SbeCnt_f},
    {MaxTblId_t,DynamicFibKeyParityStatus_t,DynamicFibKeyParityStatus_shareKeyRam6SbeCnt_f},
    {MaxTblId_t,DynamicFibKeyParityStatus_t,DynamicFibKeyParityStatus_shareKeyRam7SbeCnt_f},
    {MaxTblId_t,DynamicFibKeyParityStatus_t,DynamicFibKeyParityStatus_shareKeyRam8SbeCnt_f},
    {MaxTblId_t,DynamicMiscKeyParityStatus_t,DynamicMiscKeyParityStatus_miscKeyRam0SbeCnt_f},
    {MaxTblId_t,DynamicMiscKeyParityStatus_t,DynamicMiscKeyParityStatus_miscKeyRam1SbeCnt_f},
    {MaxTblId_t,DynamicMiscKeyParityStatus_t,DynamicMiscKeyParityStatus_miscKeyRam10SbeCnt_f},
    {MaxTblId_t,DynamicMiscKeyParityStatus_t,DynamicMiscKeyParityStatus_miscKeyRam2SbeCnt_f},
    {MaxTblId_t,DynamicMiscKeyParityStatus_t,DynamicMiscKeyParityStatus_miscKeyRam3SbeCnt_f},
    {MaxTblId_t,DynamicMiscKeyParityStatus_t,DynamicMiscKeyParityStatus_miscKeyRam4SbeCnt_f},
    {MaxTblId_t,DynamicMiscKeyParityStatus_t,DynamicMiscKeyParityStatus_miscKeyRam5SbeCnt_f},
    {MaxTblId_t,DynamicMiscKeyParityStatus_t,DynamicMiscKeyParityStatus_miscKeyRam6SbeCnt_f},
    {MaxTblId_t,DynamicMiscKeyParityStatus_t,DynamicMiscKeyParityStatus_miscKeyRam7SbeCnt_f},
    {MaxTblId_t,DynamicMiscKeyParityStatus_t,DynamicMiscKeyParityStatus_miscKeyRam8SbeCnt_f},
    {MaxTblId_t,DynamicMiscKeyParityStatus_t,DynamicMiscKeyParityStatus_miscKeyRam9SbeCnt_f},
    {MaxTblId_t,EcpuDebugStats_t,EcpuDebugStats_cpuMem3SbeCnt_f},
    {MaxTblId_t,EcpuDebugStats_t,EcpuDebugStats_cpuMem2SbeCnt_f},
    {MaxTblId_t,EcpuDebugStats_t,EcpuDebugStats_cpuMem1SbeCnt_f},
    {MaxTblId_t,EcpuDebugStats_t,EcpuDebugStats_cpuMem0SbeCnt_f},
    {InfoArbMem_t,EcpuIntfParityStatus_t,EcpuIntfParityStatus_infoArbMemSbeCnt_f},
    {PktRxArbMem_t,EcpuIntfParityStatus_t,EcpuIntfParityStatus_pktRxArbMemSbeCnt_f},
    {DsEgressScl0TcamAd_t,EgrSclHashParityStatus_t,EgrSclHashParityStatus_dsEgressScl0TcamAdSbeCnt_f},
    {DsEgressScl1TcamAd_t,EgrSclHashParityStatus_t,EgrSclHashParityStatus_dsEgressScl1TcamAdSbeCnt_f},
    {DsVlanXlateDefault_t,EgrSclHashParityStatus_t,EgrSclHashParityStatus_dsVlanXlateDefaultSbeCnt_f},
    {DsAcl0Egress_t,EpeAclOamParityStatus_t,EpeAclOamParityStatus_dsAcl0EgressSbeCnt_f},
    {DsAcl1Egress_t,EpeAclOamParityStatus_t,EpeAclOamParityStatus_dsAcl1EgressSbeCnt_f},
    {DsAcl2Egress_t,EpeAclOamParityStatus_t,EpeAclOamParityStatus_dsAcl2EgressSbeCnt_f},
    {DsAcl3Egress_t,EpeAclOamParityStatus_t,EpeAclOamParityStatus_dsAcl3EgressSbeCnt_f},
    {DsDestEthLmProfile_t,EpeAclOamParityStatus_t,EpeAclOamParityStatus_dsDestEthLmProfileSbeCnt_f},
    {MaxTblId_t,EpeAclOamParityStatus_t,EpeAclOamParityStatus_epeClaPolicingSopInfoRamSbeCnt_f},
    {EpeHdrAdjDp0EopFifo_t,EpeHdrAdjParityStatus_t,EpeHdrAdjParityStatus_epeHdrAdjDp0EopFifoSbeCnt_f},
    {EpeHdrAdjDp1EopFifo_t,EpeHdrAdjParityStatus_t,EpeHdrAdjParityStatus_epeHdrAdjDp1EopFifoSbeCnt_f},
    {DsPortLinkAgg_t,EpeHdrEditParityStatus_t,EpeHdrEditParityStatus_dsPortLinkAggSbeCnt_f},
    {DsLatencyMon0_t,EpeHdrProcParityStatus_t,EpeHdrProcParityStatus_dsLatencyMon0SbeCnt_f},
    {DsLatencyMon1_t,EpeHdrProcParityStatus_t,EpeHdrProcParityStatus_dsLatencyMon1SbeCnt_f},
    {DsDestChannel_t,EpeHdrProcParityStatus_t,EpeHdrProcParityStatus_dsDestChannelSbeCnt_f},
    {DsDestPortLoadMetric_t,EpeHdrProcParityStatus_t,EpeHdrProcParityStatus_dsDestPortLoadMetricSbeCnt_f},
    {DsEgressPortMac_t,EpeHdrProcParityStatus_t,EpeHdrProcParityStatus_dsEgressPortMacSbeCnt_f},
    {DsEgressVsi_t,EpeHdrProcParityStatus_t,EpeHdrProcParityStatus_dsEgressVsiSbeCnt_f},
    {DsFlexEditInsertHeaderTemplate_t,EpeHdrProcParityStatus_t,EpeHdrProcParityStatus_dsFlexEditInsertHeaderTemplateSbeCnt_f},
    {DsFlexEditTemplate3_t,EpeHdrProcParityStatus_t,EpeHdrProcParityStatus_dsFlexEditTemplate3SbeCnt_f},
    {DsIntExtRewriteProfile_t,EpeHdrProcParityStatus_t,EpeHdrProcParityStatus_dsIntExtRewriteProfileSbeCnt_f},
    {DsIntSessionEdit_t,EpeHdrProcParityStatus_t,EpeHdrProcParityStatus_dsIntSessionEditSbeCnt_f},
    {DsL2Edit6WOuter_t,EpeHdrProcParityStatus_t,EpeHdrProcParityStatus_dsL2Edit6WOuterSbeCnt_f},
    {DsMplsEvpnEsLabel_t,EpeHdrProcParityStatus_t,EpeHdrProcParityStatus_dsMplsEvpnEsLabelSbeCnt_f},
    {DsPathViewDstMap_t,EpeHdrProcParityStatus_t,EpeHdrProcParityStatus_dsPathViewDstMapSbeCnt_f},
    {DsPathViewSrcMap_t,EpeHdrProcParityStatus_t,EpeHdrProcParityStatus_dsPathViewSrcMapSbeCnt_f},
    {DsQueueIdBase_t,EpeHdrProcParityStatus_t,EpeHdrProcParityStatus_dsQueueIdBaseSbeCnt_f},
    {MaxTblId_t,EpeHdrProcParityStatus_t,EpeHdrProcParityStatus_hdrProcPreRdDsFifoSbeCnt_f},
    {DsDestInterface_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_dsDestInterfaceSbeCnt_f},
    {DsDestInterfaceProfile_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_dsDestInterfaceProfileSbeCnt_f},
    {DsDestPort_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_dsDestPortSbeCnt_f},
    {DsDestStpState_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_dsDestStpStateSbeCnt_f},
    {DsDestVlan_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_dsDestVlanSbeCnt_f},
    {DsDestVlanProfile_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_dsDestVlanProfileSbeCnt_f},
    {DsDestVlanStatus_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_dsDestVlanStatusSbeCnt_f},
    {DsEgressLogicDestPort_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_dsEgressLogicDestPortSbeCnt_f},
    {DsEgressRouterMac_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_dsEgressRouterMacSbeCnt_f},
    {DsEgressVlanRangeProfile_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_dsEgressVlanRangeProfileSbeCnt_f},
    {DsGlbDestPort_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_dsGlbDestPortSbeCnt_f},
    {DsPortIsolation_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_dsPortIsolationSbeCnt_f},
    {DsVlanTagBitMap_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_dsVlanTagBitMapSbeCnt_f},
    {MaxTblId_t,EpeNextHopParityStatus_t,EpeNextHopParityStatus_eNHBypassInsideFifoSbeCnt_f},
    {EpeScheduleCalendar0Ram_t,EpeScheduleParityStatus_t,EpeScheduleParityStatus_epeScheduleCalendar0RamSbeCnt_f},
    {EpeScheduleCalendar1Ram_t,EpeScheduleParityStatus_t,EpeScheduleParityStatus_epeScheduleCalendar1RamSbeCnt_f},
    {EpeScheduleCalendar0Ram_t,EpeScheduleParityStatus_t,EpeScheduleParityStatus_epeScheduleCalendar0RamSbeCnt_f, 1},
    {EpeScheduleCalendar1Ram_t,EpeScheduleParityStatus_t,EpeScheduleParityStatus_epeScheduleCalendar1RamSbeCnt_f, 1},
    {DsMacLimitCount_t,FibAccParityStatus_t,FibAccParityStatus_dsMacLimitCountSbeCnt_f},
    {DsMacLimitThreshold_t,FibAccParityStatus_t,FibAccParityStatus_dsMacLimitThresholdSbeCnt_f},
    {FlexeMgrOhMem_t,FlexeMgrParityStatus_t,FlexeMgrParityStatus_flexeMgrOhMemSbeCnt_f},
    {FlexeMgrOhMem_t,FlexeMgrParityStatus_t,FlexeMgrParityStatus_flexeMgrOhMemSbeCnt_f, 1},
    {DsIpfixSessionRecordMem0_t,FlowAccAdParityStatus_t,FlowAccAdParityStatus_dsIpfixSessionRecordMem0SbeCnt_f},
    {DsIpfixSessionRecordMem1_t,FlowAccAdParityStatus_t,FlowAccAdParityStatus_dsIpfixSessionRecordMem1SbeCnt_f},
    {DsIpfixConfig0_t,FlowAccAdParityStatus_t,FlowAccAdParityStatus_dsIpfixConfig0SbeCnt_f},
    {FlowAccIpeAdMiscInfo_t,FlowAccAdParityStatus_t,FlowAccAdParityStatus_flowAccIpeAdMiscInfoSbeCnt_f},
    {FlowAccToDmaFifo_t,FlowAccAdParityStatus_t,FlowAccAdParityStatus_flowAccToDmaFifoSbeCnt_f},
    {DsIpfixConfig1_t,FlowAccEpeParityStatus_t,FlowAccEpeParityStatus_dsIpfixConfig1SbeCnt_f},
    {FlowAccEpeAdChanInfo_t,FlowAccEpeParityStatus_t,FlowAccEpeParityStatus_flowAccEpeAdChanInfoSbeCnt_f},
    {FlowAccEpePIFifo_t,FlowAccEpeParityStatus_t,FlowAccEpeParityStatus_flowAccEpePIFifoSbeCnt_f},
    {IpfixEngineDiscardMapCtl1_t,FlowAccEpeParityStatus_t,FlowAccEpeParityStatus_ipfixEngineDiscardMapCtl1SbeCnt_f},
    {DsIpfixSamplingCount_t,FlowAccIpeParityStatus_t,FlowAccIpeParityStatus_dsIpfixSamplingCountSbeCnt_f},
    {FlowAccIpeAdChanInfo_t,FlowAccIpeParityStatus_t,FlowAccIpeParityStatus_flowAccIpeAdChanInfoSbeCnt_f},
    {FlowAccKeyCache_t,FlowAccIpeParityStatus_t,FlowAccIpeParityStatus_flowAccKeyCacheSbeCnt_f},
    {IpfixEngineDiscardMapCtl0_t,FlowAccIpeParityStatus_t,FlowAccIpeParityStatus_ipfixEngineDiscardMapCtl0SbeCnt_f},
    {DsStatsEgressACL0_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsEgressACL0SbeCnt_f},
    {DsStatsEgressACL1_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsEgressACL1SbeCnt_f},
    {DsStatsEgressACL2_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsEgressACL2SbeCnt_f},
    {DsStatsEgressACL3_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsEgressACL3SbeCnt_f},
    {DsStatsGlobal0_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsGlobal0SbeCnt_f},
    {DsStatsGlobal1_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsGlobal1SbeCnt_f},
    {DsStatsGlobal2_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsGlobal2SbeCnt_f},
    {DsStatsGlobal3_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsGlobal3SbeCnt_f},
    {DsStatsGlobal4_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsGlobal4SbeCnt_f},
    {DsStatsGlobal5_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsGlobal5SbeCnt_f},
    {DsStatsGlobal6_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsGlobal6SbeCnt_f},
    {DsStatsGlobal7_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsGlobal7SbeCnt_f},
    {DsStatsIngressACL0_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsIngressACL0SbeCnt_f},
    {DsStatsIngressACL1_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsIngressACL1SbeCnt_f},
    {DsStatsIngressACL10_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsIngressACL10SbeCnt_f},
    {DsStatsIngressACL11_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsIngressACL11SbeCnt_f},
    {DsStatsIngressACL12_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsIngressACL12SbeCnt_f},
    {DsStatsIngressACL13_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsIngressACL13SbeCnt_f},
    {DsStatsIngressACL14_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsIngressACL14SbeCnt_f},
    {DsStatsIngressACL15_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsIngressACL15SbeCnt_f},
    {DsStatsIngressACL2_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsIngressACL2SbeCnt_f},
    {DsStatsIngressACL3_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsIngressACL3SbeCnt_f},
    {DsStatsIngressACL4_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsIngressACL4SbeCnt_f},
    {DsStatsIngressACL5_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsIngressACL5SbeCnt_f},
    {DsStatsIngressACL6_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsIngressACL6SbeCnt_f},
    {DsStatsIngressACL7_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsIngressACL7SbeCnt_f},
    {DsStatsIngressACL8_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsIngressACL8SbeCnt_f},
    {DsStatsIngressACL9_t,GlobalStatsParityStatus_t,GlobalStatsParityStatus_dsStatsIngressACL9SbeCnt_f},
    {HMacDp0L0LogFifo_t,HMacEngineParityStatus_t,HMacEngineParityStatus_hMacDp0L0LogFifoSbeCnt_f},
    {HMacDp0L0LoopFifo0_t,HMacEngineParityStatus_t,HMacEngineParityStatus_hMacDp0L0LoopFifo0SbeCnt_f},
    {HMacDp0L0LoopFifo1_t,HMacEngineParityStatus_t,HMacEngineParityStatus_hMacDp0L0LoopFifo1SbeCnt_f},
    {HMacDp0L1LogFifo_t,HMacEngineParityStatus_t,HMacEngineParityStatus_hMacDp0L1LogFifoSbeCnt_f},
    {HMacDp0L1LoopFifo0_t,HMacEngineParityStatus_t,HMacEngineParityStatus_hMacDp0L1LoopFifo0SbeCnt_f},
    {HMacDp0L1LoopFifo1_t,HMacEngineParityStatus_t,HMacEngineParityStatus_hMacDp0L1LoopFifo1SbeCnt_f},
    {HMacDp1L0LogFifo_t,HMacEngineParityStatus_t,HMacEngineParityStatus_hMacDp1L0LogFifoSbeCnt_f},
    {HMacDp1L0LoopFifo0_t,HMacEngineParityStatus_t,HMacEngineParityStatus_hMacDp1L0LoopFifo0SbeCnt_f},
    {HMacDp1L0LoopFifo1_t,HMacEngineParityStatus_t,HMacEngineParityStatus_hMacDp1L0LoopFifo1SbeCnt_f},
    {HMacDp1L1LogFifo_t,HMacEngineParityStatus_t,HMacEngineParityStatus_hMacDp1L1LogFifoSbeCnt_f},
    {HMacDp1L1LoopFifo0_t,HMacEngineParityStatus_t,HMacEngineParityStatus_hMacDp1L1LoopFifo0SbeCnt_f},
    {HMacDp1L1LoopFifo1_t,HMacEngineParityStatus_t,HMacEngineParityStatus_hMacDp1L1LoopFifo1SbeCnt_f},
    {DsAcl0Ingress_t,IpeAclParityStatus_t,IpeAclParityStatus_dsAcl0IngressSbeCnt_f},
    {DsAcl10Ingress_t,IpeAclParityStatus_t,IpeAclParityStatus_dsAcl10IngressSbeCnt_f},
    {DsAcl11Ingress_t,IpeAclParityStatus_t,IpeAclParityStatus_dsAcl11IngressSbeCnt_f},
    {DsAcl12Ingress_t,IpeAclParityStatus_t,IpeAclParityStatus_dsAcl12IngressSbeCnt_f},
    {DsAcl13Ingress_t,IpeAclParityStatus_t,IpeAclParityStatus_dsAcl13IngressSbeCnt_f},
    {DsAcl14Ingress_t,IpeAclParityStatus_t,IpeAclParityStatus_dsAcl14IngressSbeCnt_f},
    {DsAcl15Ingress_t,IpeAclParityStatus_t,IpeAclParityStatus_dsAcl15IngressSbeCnt_f},
    {DsAcl1Ingress_t,IpeAclParityStatus_t,IpeAclParityStatus_dsAcl1IngressSbeCnt_f},
    {DsAcl2Ingress_t,IpeAclParityStatus_t,IpeAclParityStatus_dsAcl2IngressSbeCnt_f},
    {DsAcl3Ingress_t,IpeAclParityStatus_t,IpeAclParityStatus_dsAcl3IngressSbeCnt_f},
    {DsAcl4Ingress_t,IpeAclParityStatus_t,IpeAclParityStatus_dsAcl4IngressSbeCnt_f},
    {DsAcl5Ingress_t,IpeAclParityStatus_t,IpeAclParityStatus_dsAcl5IngressSbeCnt_f},
    {DsAcl6Ingress_t,IpeAclParityStatus_t,IpeAclParityStatus_dsAcl6IngressSbeCnt_f},
    {DsAcl7Ingress_t,IpeAclParityStatus_t,IpeAclParityStatus_dsAcl7IngressSbeCnt_f},
    {DsAcl8Ingress_t,IpeAclParityStatus_t,IpeAclParityStatus_dsAcl8IngressSbeCnt_f},
    {DsAcl9Ingress_t,IpeAclParityStatus_t,IpeAclParityStatus_dsAcl9IngressSbeCnt_f},
    {DsAclVlanActionProfile_t,IpeAclParityStatus_t,IpeAclParityStatus_dsAclVlanActionProfileSbeCnt_f},
    {DsCategoryIdPairHashLeftAd_t,IpeAclParityStatus_t,IpeAclParityStatus_dsCategoryIdPairHashLeftAdSbeCnt_f},
    {DsCategoryIdPairHashLeftKey_t,IpeAclParityStatus_t,IpeAclParityStatus_dsCategoryIdPairHashLeftKeySbeCnt_f},
    {DsCategoryIdPairHashRightAd_t,IpeAclParityStatus_t,IpeAclParityStatus_dsCategoryIdPairHashRightAdSbeCnt_f},
    {DsCategoryIdPairHashRightKey_t,IpeAclParityStatus_t,IpeAclParityStatus_dsCategoryIdPairHashRightKeySbeCnt_f},
    {DsCategoryIdPairTcamAd_t,IpeAclParityStatus_t,IpeAclParityStatus_dsCategoryIdPairTcamAdSbeCnt_f},
    {DsDestMapProfileUc_t,IpeAclParityStatus_t,IpeAclParityStatus_dsDestMapProfileUcSbeCnt_f},
    {DsSrcChannel_t,IpeAclParityStatus_t,IpeAclParityStatus_dsSrcChannelSbeCnt_f},
    {IpeFwdExcepGroupMap_t,IpeAclParityStatus_t,IpeAclParityStatus_ipeFwdExcepGroupMapSbeCnt_f},
    {DsChannelToEcmpGroupMap_t,IpeFwdParityStatus_t,IpeFwdParityStatus_dsChannelToEcmpGroupMapSbeCnt_f},
    {DsIpePhbMutationCosMap_t,IpeFwdParityStatus_t,IpeFwdParityStatus_dsIpePhbMutationCosMapSbeCnt_f},
    {DsIpePhbMutationDscpMap_t,IpeFwdParityStatus_t,IpeFwdParityStatus_dsIpePhbMutationDscpMapSbeCnt_f},
    {DsIpePolicerGroup_t,IpeFwdParityStatus_t,IpeFwdParityStatus_dsIpePolicerGroupSbeCnt_f},
    {DsPortBasedHashProfile0_t,IpeFwdParityStatus_t,IpeFwdParityStatus_dsPortBasedHashProfile0SbeCnt_f},
    {DsPhyPort_t,IpeHdrAdjParityStatus_t,IpeHdrAdjParityStatus_dsPhyPortSbeCnt_f},
    {DsPhyPortExt_t,IpeHdrAdjParityStatus_t,IpeHdrAdjParityStatus_dsPhyPortExtSbeCnt_f},
    {DsRouterMacTcamAd_t,IpeHdrAdjParityStatus_t,IpeHdrAdjParityStatus_dsRouterMacTcamAdSbeCnt_f},
    {DsVlanActionProfile_t,IpeHdrAdjParityStatus_t,IpeHdrAdjParityStatus_dsVlanActionProfileSbeCnt_f},
    {DsVlanRangeProfile_t,IpeHdrAdjParityStatus_t,IpeHdrAdjParityStatus_dsVlanRangeProfileSbeCnt_f},
    {DsVlanRangeProfile1_t,IpeHdrAdjParityStatus_t,IpeHdrAdjParityStatus_dsVlanRangeProfile1SbeCnt_f},
    {DsSrcInterface_t,IpeIntfMapParityStatus_t,IpeIntfMapParityStatus_dsSrcInterfaceSbeCnt_f},
    {DsSrcInterfaceProfile_t,IpeIntfMapParityStatus_t,IpeIntfMapParityStatus_dsSrcInterfaceProfileSbeCnt_f},
    {DsSrcPort_t,IpeIntfMapParityStatus_t,IpeIntfMapParityStatus_dsSrcPortSbeCnt_f},
    {DsSrcStpState_t,IpeIntfMapParityStatus_t,IpeIntfMapParityStatus_dsSrcStpStateSbeCnt_f},
    {DsSrcVlan_t,IpeIntfMapParityStatus_t,IpeIntfMapParityStatus_dsSrcVlanSbeCnt_f},
    {DsSrcVlanProfile_t,IpeIntfMapParityStatus_t,IpeIntfMapParityStatus_dsSrcVlanProfileSbeCnt_f},
    {DsSrcVlanStatus_t,IpeIntfMapParityStatus_t,IpeIntfMapParityStatus_dsSrcVlanStatusSbeCnt_f},
    {DsVlan2Ptr_t,IpeIntfMapParityStatus_t,IpeIntfMapParityStatus_dsVlan2PtrSbeCnt_f},
    {DsRouterMacInner_t,IpeLkupMgrParityStatus_t,IpeLkupMgrParityStatus_dsRouterMacInnerSbeCnt_f},
    {DsBidiPimGroup_t,IpePktProcParityStatus_t,IpePktProcParityStatus_dsBidiPimGroupSbeCnt_f},
    {DsRpf_t,IpePktProcParityStatus_t,IpePktProcParityStatus_dsRpfSbeCnt_f},
    {DsSrcEthLmProfile_t,IpePktProcParityStatus_t,IpePktProcParityStatus_dsSrcEthLmProfileSbeCnt_f},
    {DsVsi_t,IpePktProcParityStatus_t,IpePktProcParityStatus_dsVsiSbeCnt_f},
    {IpePhbDscpMap_t,IpePktProcParityStatus_t,IpePktProcParityStatus_ipePhbDscpMapSbeCnt_f},
    {DsLagDlbFlowSetTable_t,LinkAggParityStatus_t,LinkAggParityStatus_dsLagDlbFlowSetTableSbeCnt_f},
    {CflexLagLinkSelfHealingSet_t,LinkAggParityStatus_t,LinkAggParityStatus_cflexLagLinkSelfHealingSetSbeCnt_f},
    {DsLinkAggregateChannelGroup_t,LinkAggParityStatus_t,LinkAggParityStatus_dsLinkAggregateChannelGroupSbeCnt_f},
    {DsLinkAggregateChannelMember_t,LinkAggParityStatus_t,LinkAggParityStatus_dsLinkAggregateChannelMemberSbeCnt_f},
    {DsLinkAggregateChannelMemberSet_t,LinkAggParityStatus_t,LinkAggParityStatus_dsLinkAggregateChannelMemberSetSbeCnt_f},
    {DsLinkAggregateGroup_t,LinkAggParityStatus_t,LinkAggParityStatus_dsLinkAggregateGroupSbeCnt_f},
    {DsLinkAggregateMember_t,LinkAggParityStatus_t,LinkAggParityStatus_dsLinkAggregateMemberSbeCnt_f},
    {DsLinkAggregateMemberSet_t,LinkAggParityStatus_t,LinkAggParityStatus_dsLinkAggregateMemberSetSbeCnt_f},
    {DsPortBasedHashProfile1_t,LinkAggParityStatus_t,LinkAggParityStatus_dsPortBasedHashProfile1SbeCnt_f},
    {DsPortChannelLag_t,LinkAggParityStatus_t,LinkAggParityStatus_dsPortChannelLagSbeCnt_f},
    {DsSgmacMap_t,LinkAggParityStatus_t,LinkAggParityStatus_dsSgmacMapSbeCnt_f},
    {LagEngineChanQueDepthAvgS0_t,LinkAggParityStatus_t,LinkAggParityStatus_lagEngineChanQueDepthAvgS0SbeCnt_f},
    {LagEngineChanQueDepthCurS0_t,LinkAggParityStatus_t,LinkAggParityStatus_lagEngineChanQueDepthCurS0SbeCnt_f},
    {PortLagLinkSelfHealingSet_t,LinkAggParityStatus_t,LinkAggParityStatus_portLagLinkSelfHealingSetSbeCnt_f},
    {DsOamEpeLmStats_t,LmStatsParityStatus_t,LmStatsParityStatus_dsOamEpeLmStatsSbeCnt_f},
    {DsOamIpeLmStats_t,LmStatsParityStatus_t,LmStatsParityStatus_dsOamIpeLmStatsSbeCnt_f},
    {DsOamLmProtocolStats_t,LmStatsParityStatus_t,LmStatsParityStatus_dsOamLmProtocolStatsSbeCnt_f},
    {MaxTblId_t,LpmTcamParityStatus_t,LpmTcamParityStatus_lpmTcamAd0SbeCnt_f},
    {MaxTblId_t,LpmTcamParityStatus_t,LpmTcamParityStatus_lpmTcamAd1SbeCnt_f},
    {MaxTblId_t,LpmTcamParityStatus_t,LpmTcamParityStatus_lpmTcamAd2SbeCnt_f},
    {MaxTblId_t,LpmTcamParityStatus_t,LpmTcamParityStatus_lpmTcamAd3SbeCnt_f},
    {MaxTblId_t,LpmTcamParityStatus_t,LpmTcamParityStatus_lpmTcamAd4SbeCnt_f},
    {MaxTblId_t,LpmTcamParityStatus_t,LpmTcamParityStatus_lpmTcamAd5SbeCnt_f},
    {DsMacsecReceiveSaStatus_t,MacSecDecParityStatus_t,MacSecDecParityStatus_dsMacsecReceiveSaStatusSbeCnt_f},
    {DsMacsecReceiveSa_t,MacSecDecParityStatus_t,MacSecDecParityStatus_dsMacsecReceiveSaSbeCnt_f},
    {DsMacsecReceiveSc_t,MacSecDecParityStatus_t,MacSecDecParityStatus_dsMacsecReceiveScSbeCnt_f},
    {DsMacsecSrcSecY_t,MacSecDecParityStatus_t,MacSecDecParityStatus_dsMacsecSrcSecYSbeCnt_f},
    {MacDecChanInfo_t,MacSecDecParityStatus_t,MacSecDecParityStatus_macDecChanInfoSbeCnt_f},
    {MaxTblId_t,MacSecDecParityStatus_t,MacSecDecParityStatus_macDecIcvInfoSbeCnt_f},
    {DsMacsecReceiveSaStatus_t,MacSecDecParityStatus_t,MacSecDecParityStatus_dsMacsecReceiveSaStatusSbeCnt_f, 1},
    {DsMacsecReceiveSa_t,MacSecDecParityStatus_t,MacSecDecParityStatus_dsMacsecReceiveSaSbeCnt_f, 1},
    {DsMacsecReceiveSc_t,MacSecDecParityStatus_t,MacSecDecParityStatus_dsMacsecReceiveScSbeCnt_f, 1},
    {DsMacsecSrcSecY_t,MacSecDecParityStatus_t,MacSecDecParityStatus_dsMacsecSrcSecYSbeCnt_f, 1},
    {MacDecChanInfo_t,MacSecDecParityStatus_t,MacSecDecParityStatus_macDecChanInfoSbeCnt_f, 1},
    {MaxTblId_t,MacSecDecParityStatus_t,MacSecDecParityStatus_macDecIcvInfoSbeCnt_f, 1},
    {DsMacsecDestSecY_t,MacSecEncParityStatus_t,MacSecEncParityStatus_dsMacsecDestSecYSbeCnt_f},
    {DsMacsecTransmitSa_t,MacSecEncParityStatus_t,MacSecEncParityStatus_dsMacsecTransmitSaSbeCnt_f},
    {DsMacsecTransmitSaPn_t,MacSecEncParityStatus_t,MacSecEncParityStatus_dsMacsecTransmitSaPnSbeCnt_f},
    {DsMacsecTransmitSc_t,MacSecEncParityStatus_t,MacSecEncParityStatus_dsMacsecTransmitScSbeCnt_f},
    {MacSecEncChanInfo_t,MacSecEncParityStatus_t,MacSecEncParityStatus_macSecEncChanInfoSbeCnt_f},
    {MaxTblId_t,MacSecEncParityStatus_t,MacSecEncParityStatus_macSecEncIcvInfoSbeCnt_f},
    {DsMacsecDestSecY_t,MacSecEncParityStatus_t,MacSecEncParityStatus_dsMacsecDestSecYSbeCnt_f, 1},
    {DsMacsecTransmitSa_t,MacSecEncParityStatus_t,MacSecEncParityStatus_dsMacsecTransmitSaSbeCnt_f, 1},
    {DsMacsecTransmitSaPn_t,MacSecEncParityStatus_t,MacSecEncParityStatus_dsMacsecTransmitSaPnSbeCnt_f, 1},
    {DsMacsecTransmitSc_t,MacSecEncParityStatus_t,MacSecEncParityStatus_dsMacsecTransmitScSbeCnt_f, 1},
    {MacSecEncChanInfo_t,MacSecEncParityStatus_t,MacSecEncParityStatus_macSecEncChanInfoSbeCnt_f, 1},
    {MaxTblId_t,MacSecEncParityStatus_t,MacSecEncParityStatus_macSecEncIcvInfoSbeCnt_f, 1},
    {MaxTblId_t,McpuDebugStats_t,McpuDebugStats_mcuMemSbeCnt_f},
    {MaxTblId_t,McpuDebugStats_t,McpuDebugStats_mcuMemSbeCnt_f, 1},
    {MaxTblId_t,McpuDebugStats_t,McpuDebugStats_mcuMemSbeCnt_f, 2},
    {MaxTblId_t,McpuDebugStats_t,McpuDebugStats_mcuMemSbeCnt_f, 3},
    {MaxTblId_t,McpuDebugStats_t,McpuDebugStats_mcuMemSbeCnt_f, 4},
    {MaxTblId_t,McpuDebugStats_t,McpuDebugStats_mcuMemSbeCnt_f, 5},
    {MaxTblId_t,McpuDebugStats_t,McpuDebugStats_mcuMemSbeCnt_f, 6},
    {MetEofMem_t,MetFifoProcParityStatus_t,MetFifoProcParityStatus_metEofMemSbeCnt_f},
    {MetRcdMem_t,MetFifoProcParityStatus_t,MetFifoProcParityStatus_metRcdMemSbeCnt_f},
    {CutEopMsgExcpReqInfoFifo_t,MetFifoProcParityStatus_t,MetFifoProcParityStatus_cutEopMsgExcpReqInfoFifoSbeCnt_f},
    {CutEopMsgLogReqInfoFifo_t,MetFifoProcParityStatus_t,MetFifoProcParityStatus_cutEopMsgLogReqInfoFifoSbeCnt_f},
    {DsMetFifoExcp_t,MetFifoProcParityStatus_t,MetFifoProcParityStatus_dsMetFifoExcpSbeCnt_f},
    {McastEnqueueMsgFifo_t,MetFifoProcParityStatus_t,MetFifoProcParityStatus_mcastEnqueueMsgFifoSbeCnt_f},
    {MetEnqRcdFifo_t,MetFifoProcParityStatus_t,MetFifoProcParityStatus_metEnqRcdFifoSbeCnt_f},
    {MetLogReqFifo_t,MetFifoProcParityStatus_t,MetFifoProcParityStatus_metLogReqFifoSbeCnt_f},
    {MetMcastHiLoopFifo_t,MetFifoProcParityStatus_t,MetFifoProcParityStatus_metMcastHiLoopFifoSbeCnt_f},
    {MetMcastLoLoopFifo_t,MetFifoProcParityStatus_t,MetFifoProcParityStatus_metMcastLoLoopFifoSbeCnt_f},
    {MetMsgMem_t,MetFifoProcParityStatus_t,MetFifoProcParityStatus_metMsgMemSbeCnt_f},
    {DsApsBridge_t,MetFifoShareParityStatus_t,MetFifoShareParityStatus_dsApsBridgeSbeCnt_f},
    {DsDestMapProfileMc_t,MetFifoShareParityStatus_t,MetFifoShareParityStatus_dsDestMapProfileMcSbeCnt_f},
    {DsMetNonUcLagBlockMask_t,MetFifoShareParityStatus_t,MetFifoShareParityStatus_dsMetNonUcLagBlockMaskSbeCnt_f},
    {DsMetNonUcLagMemberBitmap_t,MetFifoShareParityStatus_t,MetFifoShareParityStatus_dsMetNonUcLagMemberBitmapSbeCnt_f},
    {BrDp0MetRcdCell_t,MetFifoShareParityStatus_t,MetFifoShareParityStatus_brDp0MetRcdCellSbeCnt_f},
    {BrDp1MetRcdCell_t,MetFifoShareParityStatus_t,MetFifoShareParityStatus_brDp1MetRcdCellSbeCnt_f},
    {DsMetLinkAggregatePort_t,MetFifoShareParityStatus_t,MetFifoShareParityStatus_dsMetLinkAggregatePortSbeCnt_f},
    {DsMetNonUcCflexMemberBitmap_t,MetFifoShareParityStatus_t,MetFifoShareParityStatus_dsMetNonUcCflexMemberBitmapSbeCnt_f},
    {DsMetNonUcChanLagBlockMask_t,MetFifoShareParityStatus_t,MetFifoShareParityStatus_dsMetNonUcChanLagBlockMaskSbeCnt_f},
    {DsMetPortChannelLag_t,MetFifoShareParityStatus_t,MetFifoShareParityStatus_dsMetPortChannelLagSbeCnt_f},
    {DsMetPortLagLinkSelfHealingSet_t,MetFifoShareParityStatus_t,MetFifoShareParityStatus_dsMetPortLagLinkSelfHealingSetSbeCnt_f},
    {MetMcastInfoTrackFifo_t,MetFifoShareParityStatus_t,MetFifoShareParityStatus_metMcastInfoTrackFifoSbeCnt_f},
    {DsMplsHashCamAd_t,MplsHashParityStatus_t,MplsHashParityStatus_dsMplsHashCamAdSbeCnt_f},
    {DsChannelizeMode_t,NetRxParityStatus_t,NetRxParityStatus_dsChannelizeModeSbeCnt_f},
    {NetRxCalendar0_t,NetRxParityStatus_t,NetRxParityStatus_netRxCalendar0SbeCnt_f},
    {NetRxCalendar1_t,NetRxParityStatus_t,NetRxParityStatus_netRxCalendar1SbeCnt_f},
    {NetRxCpuMacInfoFifo_t,NetRxParityStatus_t,NetRxParityStatus_netRxCpuMacInfoFifoSbeCnt_f},
    {NetRxDmaInputFifo_t,NetRxParityStatus_t,NetRxParityStatus_netRxDmaInputFifoSbeCnt_f},
    {MaxTblId_t,NetRxParityStatus_t,NetRxParityStatus_netRxFreePtr0FifoSbeCnt_f},
    {MaxTblId_t,NetRxParityStatus_t,NetRxParityStatus_netRxFreePtr1FifoSbeCnt_f},
    {MaxTblId_t,NetRxParityStatus_t,NetRxParityStatus_netRxFreePtr2FifoSbeCnt_f},
    {MaxTblId_t,NetRxParityStatus_t,NetRxParityStatus_netRxFreePtr3FifoSbeCnt_f},
    {NetRxLoop0InputFifo_t,NetRxParityStatus_t,NetRxParityStatus_netRxLoop0InputFifoSbeCnt_f},
    {NetRxLoop1InputFifo_t,NetRxParityStatus_t,NetRxParityStatus_netRxLoop1InputFifoSbeCnt_f},
    {NetRxOamInputFifo_t,NetRxParityStatus_t,NetRxParityStatus_netRxOamInputFifoSbeCnt_f},
    {DsChannelizeMode_t,NetRxParityStatus_t,NetRxParityStatus_dsChannelizeModeSbeCnt_f, 1},
    {NetRxCalendar0_t,NetRxParityStatus_t,NetRxParityStatus_netRxCalendar0SbeCnt_f, 1},
    {NetRxCalendar1_t,NetRxParityStatus_t,NetRxParityStatus_netRxCalendar1SbeCnt_f, 1},
    {NetRxCpuMacInfoFifo_t,NetRxParityStatus_t,NetRxParityStatus_netRxCpuMacInfoFifoSbeCnt_f, 1},
    {NetRxDmaInputFifo_t,NetRxParityStatus_t,NetRxParityStatus_netRxDmaInputFifoSbeCnt_f, 1},
    {MaxTblId_t,NetRxParityStatus_t,NetRxParityStatus_netRxFreePtr0FifoSbeCnt_f, 1},
    {MaxTblId_t,NetRxParityStatus_t,NetRxParityStatus_netRxFreePtr1FifoSbeCnt_f, 1},
    {MaxTblId_t,NetRxParityStatus_t,NetRxParityStatus_netRxFreePtr2FifoSbeCnt_f, 1},
    {MaxTblId_t,NetRxParityStatus_t,NetRxParityStatus_netRxFreePtr3FifoSbeCnt_f, 1},
    {NetRxLoop0InputFifo_t,NetRxParityStatus_t,NetRxParityStatus_netRxLoop0InputFifoSbeCnt_f, 1},
    {NetRxLoop1InputFifo_t,NetRxParityStatus_t,NetRxParityStatus_netRxLoop1InputFifoSbeCnt_f, 1},
    {NetRxOamInputFifo_t,NetRxParityStatus_t,NetRxParityStatus_netRxOamInputFifoSbeCnt_f, 1},
    {MaxTblId_t,NetTxParityStatus_t,NetTxParityStatus_netTxFreePtrFifo0SbeCnt_f},
    {MaxTblId_t,NetTxParityStatus_t,NetTxParityStatus_netTxFreePtrFifo1SbeCnt_f},
    {MaxTblId_t,NetTxParityStatus_t,NetTxParityStatus_netTxFreePtrFifo2SbeCnt_f},
    {MaxTblId_t,NetTxParityStatus_t,NetTxParityStatus_netTxFreePtrFifo3SbeCnt_f},
    {NetTxPktHdr0_t,NetTxParityStatus_t,NetTxParityStatus_netTxPktHdr0SbeCnt_f},
    {NetTxPktHdr1_t,NetTxParityStatus_t,NetTxParityStatus_netTxPktHdr1SbeCnt_f},
    {NetTxPktHdr2_t,NetTxParityStatus_t,NetTxParityStatus_netTxPktHdr2SbeCnt_f},
    {NetTxPktHdr3_t,NetTxParityStatus_t,NetTxParityStatus_netTxPktHdr3SbeCnt_f},
    {MaxTblId_t,NetTxParityStatus_t,NetTxParityStatus_netTxFreePtrFifo0SbeCnt_f, 1},
    {MaxTblId_t,NetTxParityStatus_t,NetTxParityStatus_netTxFreePtrFifo1SbeCnt_f, 1},
    {MaxTblId_t,NetTxParityStatus_t,NetTxParityStatus_netTxFreePtrFifo2SbeCnt_f, 1},
    {MaxTblId_t,NetTxParityStatus_t,NetTxParityStatus_netTxFreePtrFifo3SbeCnt_f, 1},
    {NetTxPktHdr0_t,NetTxParityStatus_t,NetTxParityStatus_netTxPktHdr0SbeCnt_f, 1},
    {NetTxPktHdr1_t,NetTxParityStatus_t,NetTxParityStatus_netTxPktHdr1SbeCnt_f, 1},
    {NetTxPktHdr2_t,NetTxParityStatus_t,NetTxParityStatus_netTxPktHdr2SbeCnt_f, 1},
    {NetTxPktHdr3_t,NetTxParityStatus_t,NetTxParityStatus_netTxPktHdr3SbeCnt_f, 1},
    {DsOamExcp_t,OamFwdParityStatus_t,OamFwdParityStatus_dsOamExcpSbeCnt_f},
    {DsOamHashKeyTable0_t,OamHashParityStatus_t,OamHashParityStatus_dsOamHashKeyTable0SbeCnt_f},
    {DsOamHashKeyTable1_t,OamHashParityStatus_t,OamHashParityStatus_dsOamHashKeyTable1SbeCnt_f},
    {OamHashLkupMgrInputFifo_t,OamHashParityStatus_t,OamHashParityStatus_oamHashLkupMgrInputFifoSbeCnt_f},
    {OamParserPDFifo_t,OamParserParityStatus_t,OamParserParityStatus_oamParserPDFifoSbeCnt_f},
    {DsMp_t,OamProcParityStatus_t,OamProcParityStatus_dsMpSbeCnt_f},
    {DsBfdV6Addr_t,OamProcParityStatus_t,OamProcParityStatus_dsBfdV6AddrSbeCnt_f},
    {DsMa_t,OamProcParityStatus_t,OamProcParityStatus_dsMaSbeCnt_f},
    {DsMaName_t,OamProcParityStatus_t,OamProcParityStatus_dsMaNameSbeCnt_f},
    {DsOamTwampTxCfg_t,OamProcParityStatus_t,OamProcParityStatus_dsOamTwampTxCfgSbeCnt_f},
    {DsPortProperty_t,OamProcParityStatus_t,OamProcParityStatus_dsPortPropertySbeCnt_f},
    {DsRmepHashKeyTable0_t,OamProcParityStatus_t,OamProcParityStatus_dsRmepHashKeyTable0SbeCnt_f},
    {DsRmepHashKeyTable1_t,OamProcParityStatus_t,OamProcParityStatus_dsRmepHashKeyTable1SbeCnt_f},
    {MaxTblId_t,PbCtlLeftEccStatus_t,PbCtlLeftEccStatus_pbCtlLeftDp0SbeCnt_f},
    {MaxTblId_t,PbCtlLeftEccStatus_t,PbCtlLeftEccStatus_pbCtlLeftDp1SbeCnt_f},
    {MaxTblId_t,PbCtlLeftEccStatus_t,PbCtlLeftEccStatus_pbCtlLeftDp0SbeCnt_f, 1},
    {MaxTblId_t,PbCtlLeftEccStatus_t,PbCtlLeftEccStatus_pbCtlLeftDp1SbeCnt_f, 1},
    {ProgramAclTcamDecodeResultFifo_t,ProgramAclLtidTcamParityStatus_t,ProgramAclLtidTcamParityStatus_programAclTcamDecodeResultFifoSbeCnt_f},
    {QMgrErmInfoTrackFifo_t,QMgrDeqChanParityStatus_t,QMgrDeqChanParityStatus_qMgrErmInfoTrackFifoSbeCnt_f},
    {QMgrQReadTrackFifo_t,QMgrDeqChanParityStatus_t,QMgrDeqChanParityStatus_qMgrQReadTrackFifoSbeCnt_f},
    {DsQMgrLenAdjConfig_t,QMgrDeqShpParityStatus_t,QMgrDeqShpParityStatus_dsQMgrLenAdjConfigSbeCnt_f},
    {MaxTblId_t,QMgrMsgMemParityStatus_t,QMgrMsgMemParityStatus_queEntryRamSbeCnt_f},
    {MaxTblId_t,QMgrMsgMemParityStatus_t,QMgrMsgMemParityStatus_qFreePtrRamSbeCnt_f},
    {MaxTblId_t,QMgrMsgMemParityStatus_t,QMgrMsgMemParityStatus_queEntryRamSbeCnt_f, 1},
    {MaxTblId_t,QMgrMsgMemParityStatus_t,QMgrMsgMemParityStatus_qFreePtrRamSbeCnt_f, 1},
    {MaxTblId_t,QMgrMsgMemParityStatus_t,QMgrMsgMemParityStatus_queEntryRamSbeCnt_f, 2},
    {MaxTblId_t,QMgrMsgMemParityStatus_t,QMgrMsgMemParityStatus_qFreePtrRamSbeCnt_f, 2},
    {DsCFlexDstChannelBlockMask_t,QMgrQWriteParityStatus_t,QMgrQWriteParityStatus_dsCFlexDstChannelBlockMaskSbeCnt_f},
    {DsErmChannel_t,QMgrQWriteParityStatus_t,QMgrQWriteParityStatus_dsErmChannelSbeCnt_f},
    {DsErmColorDpMap_t,QMgrQWriteParityStatus_t,QMgrQWriteParityStatus_dsErmColorDpMapSbeCnt_f},
    {DsErmPrioScTcMap_t,QMgrQWriteParityStatus_t,QMgrQWriteParityStatus_dsErmPrioScTcMapSbeCnt_f},
    {DsPortBlockMask_t,QMgrQWriteParityStatus_t,QMgrQWriteParityStatus_dsPortBlockMaskSbeCnt_f},
    {DsQueueMap_t,QMgrQWriteParityStatus_t,QMgrQWriteParityStatus_dsQueueMapSbeCnt_f},
    {MaxTblId_t,QMgrQWriteParityStatus_t,QMgrQWriteParityStatus_dsQueueMapHash0SbeCnt_f},
    {MaxTblId_t,QMgrQWriteParityStatus_t,QMgrQWriteParityStatus_dsQueueMapHash1SbeCnt_f},
    {MaxTblId_t,QMgrQWriteParityStatus_t,QMgrQWriteParityStatus_dsQueueMapHash2SbeCnt_f},
    {DsQWriteRepInit_t,QMgrQWriteParityStatus_t,QMgrQWriteParityStatus_dsQWriteRepInitSbeCnt_f},
    {MaxTblId_t,ScpuDebugStats_t,ScpuDebugStats_cpuMem3SbeCnt_f},
    {MaxTblId_t,ScpuDebugStats_t,ScpuDebugStats_cpuMem2SbeCnt_f},
    {MaxTblId_t,ScpuDebugStats_t,ScpuDebugStats_cpuMem1SbeCnt_f},
    {MaxTblId_t,ScpuDebugStats_t,ScpuDebugStats_cpuMem0SbeCnt_f},
    {ScpuPktRxArbMem_t,ScpuIntfParityStatus_t,ScpuIntfParityStatus_scpuPktRxArbMemSbeCnt_f},
    {DsFlexEApsCfg_t,SpnOamParityStatus_t,SpnOamParityStatus_dsFlexEApsCfgSbeCnt_f},
    {DsFlexE1DmStoreTable_t,SpnOamParityStatus_t,SpnOamParityStatus_dsFlexE1DmStoreTableSbeCnt_f},
    {DsFlexEDmDelayStats_t,SpnOamParityStatus_t,SpnOamParityStatus_dsFlexEDmDelayStatsSbeCnt_f},
    {DsFlexEDmmStoreTable_t,SpnOamParityStatus_t,SpnOamParityStatus_dsFlexEDmmStoreTableSbeCnt_f},
    {DsFlexEDmStoreTable_t,SpnOamParityStatus_t,SpnOamParityStatus_dsFlexEDmStoreTableSbeCnt_f},
    {DsFlexEMep_t,SpnOamParityStatus_t,SpnOamParityStatus_dsFlexEMepSbeCnt_f},
    {DsFlexEMepCfg_t,SpnOamParityStatus_t,SpnOamParityStatus_dsFlexEMepCfgSbeCnt_f},
    {DsFlexEOamBerProfile_t,SpnOamParityStatus_t,SpnOamParityStatus_dsFlexEOamBerProfileSbeCnt_f},
    {DsFlexEOamBerStats_t,SpnOamParityStatus_t,SpnOamParityStatus_dsFlexEOamBerStatsSbeCnt_f},
    {DsFlexEOamReiProfile_t,SpnOamParityStatus_t,SpnOamParityStatus_dsFlexEOamReiProfileSbeCnt_f},
    {DsFlexEOamReiStats_t,SpnOamParityStatus_t,SpnOamParityStatus_dsFlexEOamReiStatsSbeCnt_f},
    {DsFlexEOamTxScanCfg_t,SpnOamParityStatus_t,SpnOamParityStatus_dsFlexEOamTxScanCfgSbeCnt_f},
    {DsFlexEOamTxScanCounter_t,SpnOamParityStatus_t,SpnOamParityStatus_dsFlexEOamTxScanCounterSbeCnt_f},
    {DsFlexESDAPIStoreTable_t,SpnOamParityStatus_t,SpnOamParityStatus_dsFlexESDAPIStoreTableSbeCnt_f},
    {SpnOamReplyInfo_t,SpnOamParityStatus_t,SpnOamParityStatus_spnOamReplyInfoSbeCnt_f},
    {SpnOamTxInfo_t,SpnOamParityStatus_t,SpnOamParityStatus_spnOamTxInfoSbeCnt_f},
    {DsPhyPortExt2_t,UserIdHashParityStatus_t,UserIdHashParityStatus_dsPhyPortExt2SbeCnt_f},
    {DsUserIdHash0TcamAdMem_t,UserIdHashParityStatus_t,UserIdHashParityStatus_dsUserIdHash0TcamAdMemSbeCnt_f},
    {DsUserIdHash1TcamAdMem_t,UserIdHashParityStatus_t,UserIdHashParityStatus_dsUserIdHash1TcamAdMemSbeCnt_f},
    {DsUserIdTcam0AdMem_t,UserIdHashParityStatus_t,UserIdHashParityStatus_dsUserIdTcam0AdMemSbeCnt_f},
    {DsUserIdTcam1AdMem_t,UserIdHashParityStatus_t,UserIdHashParityStatus_dsUserIdTcam1AdMemSbeCnt_f},
    {MaxTblId_t, MaxTblId_t, 0}
};


uint16 drv_ecc_tmm_scan_tcam_tbl[][5] =
{
    {DRV_FTM_TCAM_KEY0,DsAclQosMacKey160Egr0_t,DsAclQosMacKey160Egr1_t,DsAclQosMacKey160Egr2_t,MaxTblId_t},
    {DRV_FTM_TCAM_KEY0,DsAclQosMacKey160Ing0_t,DsAclQosMacKey160Ing1_t,DsAclQosMacKey160Ing2_t,DsAclQosMacKey160Ing3_t},
    {DRV_FTM_TCAM_KEY0,DsAclQosMacKey160Ing4_t,DsAclQosMacKey160Ing5_t,DsAclQosMacKey160Ing6_t,DsAclQosMacKey160Ing7_t},
    {DRV_FTM_TCAM_KEY0,DsUserId0TcamKey160_t,DsUserId1TcamKey160_t,MaxTblId_t,MaxTblId_t},
    {DRV_FTM_LPM_TCAM_KEY0,DsLpmTcamIpv4HalfKey_t,MaxTblId_t ,MaxTblId_t,MaxTblId_t},
    {DRV_FTM_CID_TCAM,DsCategoryIdPairTcamKey_t,MaxTblId_t,MaxTblId_t,MaxTblId_t},
    {MaxTblId_t,MaxTblId_t,MaxTblId_t,MaxTblId_t,MaxTblId_t}
};

#define DRV_MEM_REG(name,  TYPE, SUB_TYPE, SUB_ID, id,  num, addr3w, addr6w, addr12w, E_SZ) \
    do{\
        drv_tmm_mem[id].entry_num = num;\
        drv_tmm_mem[id].addr_3w = addr3w;\
        drv_tmm_mem[id].addr_6w = addr6w;\
        drv_tmm_mem[id].addr_12w = addr12w;\
        drv_tmm_mem[id].type = TYPE;\
        drv_tmm_mem[id].sub_type = SUB_TYPE;\
        drv_tmm_mem[id].sub_id = SUB_ID;\
        drv_tmm_mem[id].entry_size = E_SZ<<2;\
     }while(0)

#define DRV_MEM_REG_TCAM(name,  TYPE, SUB_TYPE, SUB_ID, id,  num, addr3w, addr6w, addr12w, TMID) \
    do{\
        drv_tmm_mem[id].entry_num = num;\
        drv_tmm_mem[id].addr_3w = addr3w;\
        drv_tmm_mem[id].addr_6w = addr6w;\
        drv_tmm_mem[id].addr_12w = addr12w;\
        drv_tmm_mem[id].type = TYPE;\
        drv_tmm_mem[id].sub_type = SUB_TYPE;\
        drv_tmm_mem[id].sub_id = SUB_ID;\
        drv_tmm_mem[id].tcam_map_id = TMID;\
     }while(0)


#define DynamicFibKeyShareRamAddrBase       TABLE_INFO(lchip, DynamicFibKeyShareRam16W_t).addrs[0]
#define DynamicFibKeyAntFlowAddrBase        TABLE_INFO(lchip, DynamicFibKeyAntFlow_t).addrs[0]
#define DynamicMiscKeyShareRamAddrBase      TABLE_INFO(lchip, DynamicMiscKeyShareRam16W_t).addrs[0]
#define DynamicMiscKeyMplsHashAddrBase      TABLE_INFO(lchip, DynamicMiscKeyMplsHash16W_t).addrs[0]
#define DynamicAdShareRamAddrBase           TABLE_INFO(lchip, DynamicAdShareRam16W_t).addrs[0]
#define DynamicAdGemPortAddrBase            TABLE_INFO(lchip, DynamicAdGemPort16W_t).addrs[0]
#define DynamicEditShareRamAddrBase         TABLE_INFO(lchip, DynamicEditShareRam16W_t).addrs[0]
#define QueueHashRamAddrBase                TABLE_INFO(lchip, DsQueueMapHashKeyTable_t).addrs[0]

#define DynamicFibKeyShareRamBlockBase(B)   (DynamicFibKeyShareRamAddrBase  + (B<<21))
#define DynamicFibKeyAntFlowBlockBase(B)    (DynamicFibKeyAntFlowAddrBase   + (B<<20))
#define DynamicMiscKeyShareRamBlockBase(B)  (DynamicMiscKeyShareRamAddrBase + (B<<18))
#define DynamicMiscKeyMplsHashBlockBase(B)  (DynamicMiscKeyMplsHashAddrBase + (B<<18))
#define DynamicAdShareRamBlockBase(B)       (DynamicAdShareRamAddrBase      + (B<<21))
#define DynamicAdGemPortBlockBase(B)        (DynamicAdGemPortAddrBase       + (B<<21))
#define DynamicEditShareRamBlockBase(B)     (DynamicEditShareRamAddrBase    + (B<<20))
#define QueueHashRamBlockBase(B)            (QueueHashRamAddrBase           + (B<<15))

#define _________FLOW_TCAM_MEM_ADDR_________

#define IgrSclTcam0KeyBlockBase(B)          (TABLE_INFO(lchip, UserIdHashTcamMem_t).addrs[0] + (B<<9)*TABLE_ENTRY_OFFSET(lchip, UserIdHashTcamMem_t))
#define IgrSclTcam1KeyBlockBase(B)          (TABLE_INFO(lchip, UserIdTcamMem_t).addrs[0] + (B<<10)*TABLE_ENTRY_OFFSET(lchip, UserIdTcamMem_t))
#define IgrAclTcamKeyBlockBase(B)           (TABLE_INFO(lchip, ProgramAclTcamMem_t).addrs[0] + (B<<11)*TABLE_ENTRY_OFFSET(lchip, ProgramAclTcamMem_t))
#define EgrAclTcamKeyBlockBase(B)           (TABLE_INFO(lchip, EgressAclTcamTcamMem_t).addrs[0] + (B<<10)*TABLE_ENTRY_OFFSET(lchip, EgressAclTcamTcamMem_t))
#define EgrSclTcamKeyBlockBase(B)           (TABLE_INFO(lchip, EgrSclHashTcamMem_t).addrs[0] + (B<<8)*TABLE_ENTRY_OFFSET(lchip, EgrSclHashTcamMem_t))
#define LpmTcam0KeyBlockBase(B)             (TABLE_INFO(lchip, LpmTcamTcamMem_t).addrs[0] + (B<<12)*TABLE_ENTRY_OFFSET(lchip, LpmTcamTcamMem_t))
#define LpmTcam1KeyBlockBase(B)             (LpmTcam0KeyBlockBase(8) + (B<<13)*TABLE_ENTRY_OFFSET(lchip, LpmTcamTcamMem_t))

/* program acl tcam addr is not continuous. */
#define IgrAclTcamAdBlockBase(B)            (TABLE_INFO(lchip, DsAclIngress_t).addrs[0] + (B*2048)*DRV_ADDR_BYTES_PER_ENTRY*2)
/* egress acl tcam ad size is 5w. */
#define EgrAclTcamAdBlockBase(B)            (TABLE_INFO(lchip, DsAclEgress_t).addrs[0]  + (B<<10)*DRV_ADDR_BYTES_PER_ENTRY*2)

#define _________LPM_TCAM_MEM_ADDR_________

#define DRV_LPM_TCAM_AD0_BASE(B)            (TABLE_INFO(lchip, LpmTcamAdMem_t).addrs[0] + (B<<12)*DRV_LPM_AD0_BYTE_PER_ENTRY)
#define DRV_LPM_TCAM_AD1_BASE(B)            (DRV_LPM_TCAM_AD0_BASE(8) + (B<<13)*DRV_LPM_AD1_BYTE_PER_ENTRY)

#if (SDK_WORK_PLATFORM == 1)
extern int32
cm_mem_model_parse_cutdown_file(uint32* spec_arr, uint8 from_drv);

static void
_drv_tmm_mem_cutdown(uint8 lchip)
{
    uint32 spec_arr[DRV_FTM_MAX_ID] = {0};

    if (cm_mem_model_parse_cutdown_file(spec_arr, 1) < 0)
    {
        return;
    }
    DRV_MEM_REG("IpfixKey",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_IPFIX,  0,  DRV_FTM_SRAM43, spec_arr[DRV_FTM_SRAM43],  TABLE_INFO(lchip, DsIpfixHashKeyTable12W_t).addrs[0],  0, 0, 16);

    DRV_MEM_REG_TCAM("Tcam key0",  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_SCL0_KEY,  0,  DRV_FTM_TCAM_KEY0,  spec_arr[DRV_FTM_TCAM_KEY0],    IgrSclTcam0KeyBlockBase(0), 0, 0, 0);
    DRV_MEM_REG_TCAM("Tcam key1",  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_SCL0_KEY,  1,  DRV_FTM_TCAM_KEY1,  spec_arr[DRV_FTM_TCAM_KEY1],    IgrSclTcam0KeyBlockBase(0), 0, 0, 0);
    DRV_MEM_REG_TCAM("Tcam key2",  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_SCL1_KEY,  0,  DRV_FTM_TCAM_KEY2,  2*spec_arr[DRV_FTM_TCAM_KEY2],  IgrSclTcam1KeyBlockBase(0), 0, 0, 1);
    DRV_MEM_REG_TCAM("Tcam key3",  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_SCL0_KEY,  1,  DRV_FTM_TCAM_KEY3,  2*spec_arr[DRV_FTM_TCAM_KEY3],  IgrSclTcam1KeyBlockBase(1), 0, 0, 1);
    DRV_MEM_REG_TCAM("Tcam key4",  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   0,  DRV_FTM_TCAM_KEY4,  2*spec_arr[DRV_FTM_TCAM_KEY4],  IgrAclTcamKeyBlockBase(0),  0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key5",  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   1,  DRV_FTM_TCAM_KEY5,  2*spec_arr[DRV_FTM_TCAM_KEY5],  IgrAclTcamKeyBlockBase(1),  0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key6",  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   2,  DRV_FTM_TCAM_KEY6,  2*spec_arr[DRV_FTM_TCAM_KEY6],  IgrAclTcamKeyBlockBase(2),  0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key7",  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   3,  DRV_FTM_TCAM_KEY7,  2*spec_arr[DRV_FTM_TCAM_KEY7],  IgrAclTcamKeyBlockBase(3),  0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key8",  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   4,  DRV_FTM_TCAM_KEY8,  2*spec_arr[DRV_FTM_TCAM_KEY8],  IgrAclTcamKeyBlockBase(4),  0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key9",  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   5,  DRV_FTM_TCAM_KEY9,  2*spec_arr[DRV_FTM_TCAM_KEY9],  IgrAclTcamKeyBlockBase(5),  0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key10", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   6,  DRV_FTM_TCAM_KEY10, 2*spec_arr[DRV_FTM_TCAM_KEY10], IgrAclTcamKeyBlockBase(6),  0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key11", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   7,  DRV_FTM_TCAM_KEY11, 2*spec_arr[DRV_FTM_TCAM_KEY11], IgrAclTcamKeyBlockBase(7),  0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key12", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   8,  DRV_FTM_TCAM_KEY12, 2*spec_arr[DRV_FTM_TCAM_KEY12], IgrAclTcamKeyBlockBase(8),  0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key13", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   9,  DRV_FTM_TCAM_KEY13, 2*spec_arr[DRV_FTM_TCAM_KEY13], IgrAclTcamKeyBlockBase(9),  0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key14", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   10, DRV_FTM_TCAM_KEY14, 2*spec_arr[DRV_FTM_TCAM_KEY14], IgrAclTcamKeyBlockBase(10), 0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key15", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   11, DRV_FTM_TCAM_KEY15, 2*spec_arr[DRV_FTM_TCAM_KEY15], IgrAclTcamKeyBlockBase(11), 0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key16", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   12, DRV_FTM_TCAM_KEY16, 2*spec_arr[DRV_FTM_TCAM_KEY16], IgrAclTcamKeyBlockBase(12), 0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key17", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   13, DRV_FTM_TCAM_KEY17, 2*spec_arr[DRV_FTM_TCAM_KEY17], IgrAclTcamKeyBlockBase(13), 0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key18", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   14, DRV_FTM_TCAM_KEY18, 2*spec_arr[DRV_FTM_TCAM_KEY18], IgrAclTcamKeyBlockBase(14), 0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key19", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   15, DRV_FTM_TCAM_KEY19, 2*spec_arr[DRV_FTM_TCAM_KEY19], IgrAclTcamKeyBlockBase(15), 0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key20", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_E_ACL_KEY,   0,  DRV_FTM_TCAM_KEY20, 2*spec_arr[DRV_FTM_TCAM_KEY20], EgrAclTcamKeyBlockBase(0),  0, 0, 3);
    DRV_MEM_REG_TCAM("Tcam key21", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_E_ACL_KEY,   1,  DRV_FTM_TCAM_KEY21, 2*spec_arr[DRV_FTM_TCAM_KEY21], EgrAclTcamKeyBlockBase(1),  0, 0, 3);
    DRV_MEM_REG_TCAM("Tcam key22", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_E_ACL_KEY,   2,  DRV_FTM_TCAM_KEY22, 2*spec_arr[DRV_FTM_TCAM_KEY22], EgrAclTcamKeyBlockBase(2),  0, 0, 3);
    DRV_MEM_REG_TCAM("Tcam key23", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_E_ACL_KEY,   3,  DRV_FTM_TCAM_KEY23, 2*spec_arr[DRV_FTM_TCAM_KEY23], EgrAclTcamKeyBlockBase(3),  0, 0, 3);
    DRV_MEM_REG_TCAM("Tcam key24", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_E_SCL_KEY,   0,  DRV_FTM_TCAM_KEY24, spec_arr[DRV_FTM_TCAM_KEY24],   EgrSclTcamKeyBlockBase(0),  0, 0, 4);
    DRV_MEM_REG_TCAM("Tcam key25", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_E_SCL_KEY,   1,  DRV_FTM_TCAM_KEY25, spec_arr[DRV_FTM_TCAM_KEY25],   EgrSclTcamKeyBlockBase(1),  0, 0, 4);

    DRV_MEM_REG_TCAM("LPM key0" ,  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_LPM_KEY,  0,  DRV_FTM_LPM_TCAM_KEY0, 2*spec_arr[DRV_FTM_LPM_TCAM_KEY0], LpmTcam0KeyBlockBase(0), 0, 0, 5);
    DRV_MEM_REG_TCAM("LPM key1" ,  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_LPM_KEY,  1,  DRV_FTM_LPM_TCAM_KEY1, 2*spec_arr[DRV_FTM_LPM_TCAM_KEY1], LpmTcam0KeyBlockBase(1), 0, 0, 5);
    DRV_MEM_REG_TCAM("LPM key2" ,  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_LPM_KEY,  2,  DRV_FTM_LPM_TCAM_KEY2, 2*spec_arr[DRV_FTM_LPM_TCAM_KEY2], LpmTcam0KeyBlockBase(2), 0, 0, 5);
    DRV_MEM_REG_TCAM("LPM key3" ,  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_LPM_KEY,  3,  DRV_FTM_LPM_TCAM_KEY3, 2*spec_arr[DRV_FTM_LPM_TCAM_KEY3], LpmTcam0KeyBlockBase(3), 0, 0, 5);
    DRV_MEM_REG_TCAM("LPM key4" ,  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_LPM_KEY,  4,  DRV_FTM_LPM_TCAM_KEY4, 2*spec_arr[DRV_FTM_LPM_TCAM_KEY4], LpmTcam1KeyBlockBase(0), 0, 0, 5);
    DRV_MEM_REG_TCAM("LPM key5" ,  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_LPM_KEY,  5,  DRV_FTM_LPM_TCAM_KEY5, 2*spec_arr[DRV_FTM_LPM_TCAM_KEY5], LpmTcam1KeyBlockBase(1), 0, 0, 5);
}

#endif

#if (SDK_WORK_PLATFORM == 1)
int32
drv_mem_init_tmm(uint8 lchip)
{
    DRV_MEM_REG("KeySram0",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  0,   DRV_FTM_SRAM0, 4*4*1024,  DynamicFibKeyShareRamBlockBase(0), 0, 0, 12);
    DRV_MEM_REG("KeySram1",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  1,   DRV_FTM_SRAM1, 4*4*1024,  DynamicFibKeyShareRamBlockBase(1), 0, 0, 12);
    DRV_MEM_REG("KeySram2",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  2,   DRV_FTM_SRAM2, 4*16*1024, DynamicFibKeyShareRamBlockBase(2), 0, 0, 12);
    DRV_MEM_REG("KeySram3",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  3,   DRV_FTM_SRAM3, 4*16*1024, DynamicFibKeyShareRamBlockBase(3), 0, 0, 12);
    DRV_MEM_REG("KeySram4",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  4,   DRV_FTM_SRAM4, 4*16*1024, DynamicFibKeyShareRamBlockBase(4), 0, 0, 12);
    DRV_MEM_REG("KeySram5",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  5,   DRV_FTM_SRAM5, 4*16*1024, DynamicFibKeyShareRamBlockBase(5), DynamicFibKeyAntFlowBlockBase(0), 0, 12);
    DRV_MEM_REG("KeySram6",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  6,   DRV_FTM_SRAM6, 4*16*1024, DynamicFibKeyShareRamBlockBase(6), DynamicFibKeyAntFlowBlockBase(1), 0, 12);
    DRV_MEM_REG("KeySram7",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  7,   DRV_FTM_SRAM7, 4*2*1024,  DynamicFibKeyShareRamBlockBase(7), 0, 0, 12);
    DRV_MEM_REG("KeySram8",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  8,   DRV_FTM_SRAM8, 4*2*1024,  DynamicFibKeyShareRamBlockBase(8), 0, 0, 12);

    DRV_MEM_REG("KeySram9",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  9,   DRV_FTM_SRAM9,  4*2*1024, DynamicMiscKeyShareRamBlockBase(0),  DynamicMiscKeyMplsHashBlockBase(0), 0, 12);
    DRV_MEM_REG("KeySram10",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  10,  DRV_FTM_SRAM10, 4*2*1024, DynamicMiscKeyShareRamBlockBase(1),  DynamicMiscKeyMplsHashBlockBase(1), 0, 12);
    DRV_MEM_REG("KeySram11",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  11,  DRV_FTM_SRAM11, 4*4*1024, DynamicMiscKeyShareRamBlockBase(2),  0, 0, 12);
    DRV_MEM_REG("KeySram12",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  12,  DRV_FTM_SRAM12, 4*4*1024, DynamicMiscKeyShareRamBlockBase(3),  0, 0, 12);
    DRV_MEM_REG("KeySram13",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  13,  DRV_FTM_SRAM13, 4*2*1024, DynamicMiscKeyShareRamBlockBase(4),  0, 0, 12);
    DRV_MEM_REG("KeySram14",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  14,  DRV_FTM_SRAM14, 4*2*1024, DynamicMiscKeyShareRamBlockBase(5),  0, 0, 12);
    DRV_MEM_REG("KeySram15",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  15,  DRV_FTM_SRAM15, 4*2*1024, DynamicMiscKeyShareRamBlockBase(6),  0, 0, 12);
    DRV_MEM_REG("KeySram16",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  16,  DRV_FTM_SRAM16, 4*2*1024, DynamicMiscKeyShareRamBlockBase(7),  0, 0, 12);
    DRV_MEM_REG("KeySram17",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  17,  DRV_FTM_SRAM17, 4*2*1024, DynamicMiscKeyShareRamBlockBase(8),  0, 0, 12);
    DRV_MEM_REG("KeySram18",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  18,  DRV_FTM_SRAM18, 4*2*1024, DynamicMiscKeyShareRamBlockBase(9),  0, 0, 12);
    DRV_MEM_REG("KeySram19",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  19,  DRV_FTM_SRAM19, 4*2*1024, DynamicMiscKeyShareRamBlockBase(10), 0, 0, 12);

    DRV_MEM_REG("AdSram0",    DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_AD,  0,    DRV_FTM_SRAM20, 4*16*1024, DynamicAdShareRamBlockBase(0), 0, 0, 16);
    DRV_MEM_REG("AdSram1",    DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_AD,  1,    DRV_FTM_SRAM21, 4*8*1024,  DynamicAdShareRamBlockBase(1), 0, 0, 16);
    DRV_MEM_REG("AdSram2",    DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_AD,  2,    DRV_FTM_SRAM22, 4*8*1024,  DynamicAdShareRamBlockBase(2), 0, 0, 16);
    DRV_MEM_REG("AdSram3",    DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_AD,  3,    DRV_FTM_SRAM23, 4*4*1024,  DynamicAdShareRamBlockBase(3), 0, 0, 16);
    DRV_MEM_REG("AdSram4",    DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_AD,  4,    DRV_FTM_SRAM24, 4*4*1024,  DynamicAdShareRamBlockBase(4), DynamicAdGemPortBlockBase(4), 0, 16);
    DRV_MEM_REG("AdSram5",    DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_AD,  5,    DRV_FTM_SRAM25, 4*2*1024,  DynamicAdShareRamBlockBase(5), DynamicAdGemPortBlockBase(5), 0, 16);
    DRV_MEM_REG("AdSram6",    DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_AD,  6,    DRV_FTM_SRAM26, 4*2*1024,  DynamicAdShareRamBlockBase(6), DynamicAdGemPortBlockBase(6), 0, 16);

    DRV_MEM_REG("EditSram0",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_EDIT,  0,  DRV_FTM_SRAM27, 4*16*1024, DynamicEditShareRamBlockBase(0), 0, 0, 16);
    DRV_MEM_REG("EditSram1",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_EDIT,  1,  DRV_FTM_SRAM28, 4*8*1024,  DynamicEditShareRamBlockBase(1), 0, 0, 16);
    DRV_MEM_REG("EditSram2",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_EDIT,  2,  DRV_FTM_SRAM29, 4*4*1024,  DynamicEditShareRamBlockBase(2), 0, 0, 16);
    DRV_MEM_REG("EditSram3",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_EDIT,  3,  DRV_FTM_SRAM30, 4*4*1024,  DynamicEditShareRamBlockBase(3), 0, 0, 16);
    DRV_MEM_REG("EditSram4",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_EDIT,  4,  DRV_FTM_SRAM31, 4*2*1024,  DynamicEditShareRamBlockBase(4), 0, 0, 16);
    DRV_MEM_REG("EditSram5",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_EDIT,  5,  DRV_FTM_SRAM32, 4*2*1024,  DynamicEditShareRamBlockBase(5), 0, 0, 16);

    DRV_MEM_REG("OamSram0",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_OAM,  0,   DRV_FTM_SRAM33, 4*256,     TABLE_INFO(lchip, DsRmepHashKeyTable0_t).addrs[0], 0, 0, 8);
    DRV_MEM_REG("OamSram1",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_OAM,  1,   DRV_FTM_SRAM34, 4*256,     TABLE_INFO(lchip, DsRmepHashKeyTable1_t).addrs[0], 0, 0, 8);
    DRV_MEM_REG("OamSram2",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_OAM,  2,   DRV_FTM_SRAM35, 8*2*1024,  TABLE_INFO(lchip, DsMp_t).addrs[0],                0, 0, 6);
    DRV_MEM_REG("OamSram3",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_OAM,  3,   DRV_FTM_SRAM36, 4*1*1024,  TABLE_INFO(lchip, DsMa_t).addrs[0],                0, 0, 3);
    DRV_MEM_REG("OamSram4",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_OAM,  4,   DRV_FTM_SRAM37, 4*1*1024,  TABLE_INFO(lchip, DsMaName_t).addrs[0],            0, 0, 4);
    DRV_MEM_REG("OamSram5",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_OAM,  5,   DRV_FTM_SRAM38, 4*1*1024,  TABLE_INFO(lchip, DsOamHashKeyTable0_t).addrs[0],  0, 0, 12);
    DRV_MEM_REG("OamSram6",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_OAM,  6,   DRV_FTM_SRAM39, 4*1*1024,  TABLE_INFO(lchip, DsOamHashKeyTable1_t).addrs[0],  0, 0, 12);

    DRV_MEM_REG("QueSram0",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_QUEUE,  0,  DRV_FTM_SRAM40, 4096,      QueueHashRamBlockBase(0), 0, 0, 4);
    DRV_MEM_REG("QueSram1",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_QUEUE,  1,  DRV_FTM_SRAM41, 4096,      QueueHashRamBlockBase(1), 0, 0, 4);
    DRV_MEM_REG("QueSram2",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_QUEUE,  2,  DRV_FTM_SRAM42, 4096,      QueueHashRamBlockBase(2), 0, 0, 4);

    DRV_MEM_REG("IpfixKey",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_IPFIX,  0,  DRV_FTM_SRAM43, 256*1024,  TABLE_INFO(lchip, DsIpfixHashKeyTable12W_t).addrs[0],  0, 0, 16);
    DRV_MEM_REG("IpfixAd0",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_IPFIX,  1,  DRV_FTM_SRAM44, 256*1024,  TABLE_INFO(lchip, DsIpfixSessionRecordMem0_t).addrs[0], 0, 0, 8);
    DRV_MEM_REG("IpfixAd1",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_IPFIX,  2,  DRV_FTM_SRAM45, 256*1024,  TABLE_INFO(lchip, DsIpfixSessionRecordMem1_t).addrs[0], 0, 0, 8);

    DRV_MEM_REG_TCAM("Tcam key0",  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_SCL0_KEY,  0,  DRV_FTM_TCAM_KEY0,  512,    0x00000000, 0, 0, 0);
    DRV_MEM_REG_TCAM("Tcam key1",  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_SCL0_KEY,  1,  DRV_FTM_TCAM_KEY1,  512,    0x01000000, 0, 0, 0);
    DRV_MEM_REG_TCAM("Tcam key2",  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_SCL1_KEY,  0,  DRV_FTM_TCAM_KEY2,  2*1024, 0x02000000, 0, 0, 1);
    DRV_MEM_REG_TCAM("Tcam key3",  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_SCL1_KEY,  1,  DRV_FTM_TCAM_KEY3,  2*1024, 0x03000000, 0, 0, 1);
    DRV_MEM_REG_TCAM("Tcam key4",  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   0,  DRV_FTM_TCAM_KEY4,  2*2048, 0x04000000,  0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key5",  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   1,  DRV_FTM_TCAM_KEY5,  2*2048, 0x05000000,  0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key6",  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   2,  DRV_FTM_TCAM_KEY6,  2*2048, 0x06000000,  0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key7",  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   3,  DRV_FTM_TCAM_KEY7,  2*2048, 0x07000000,  0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key8",  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   4,  DRV_FTM_TCAM_KEY8,  2*2048, 0x08000000,  0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key9",  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   5,  DRV_FTM_TCAM_KEY9,  2*2048, 0x09000000,  0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key10", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   6,  DRV_FTM_TCAM_KEY10, 2*2048, 0x0A000000,  0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key11", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   7,  DRV_FTM_TCAM_KEY11, 2*2048, 0x0B000000,  0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key12", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   8,  DRV_FTM_TCAM_KEY12, 2*2048, 0x0C000000,  0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key13", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   9,  DRV_FTM_TCAM_KEY13, 2*2048, 0x0D000000,  0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key14", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   10, DRV_FTM_TCAM_KEY14, 2*2048, 0x0E000000, 0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key15", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   11, DRV_FTM_TCAM_KEY15, 2*2048, 0x0F000000, 0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key16", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   12, DRV_FTM_TCAM_KEY16, 2*2048, 0x10000000, 0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key17", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   13, DRV_FTM_TCAM_KEY17, 2*2048, 0x11000000, 0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key18", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   14, DRV_FTM_TCAM_KEY18, 2*2048, 0x12000000, 0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key19", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   15, DRV_FTM_TCAM_KEY19, 2*2048, 0x13000000, 0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key20", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_E_ACL_KEY,   0,  DRV_FTM_TCAM_KEY20, 2*1024, 0x14000000,  0, 0, 3);
    DRV_MEM_REG_TCAM("Tcam key21", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_E_ACL_KEY,   1,  DRV_FTM_TCAM_KEY21, 2*1024, 0x15000000,  0, 0, 3);
    DRV_MEM_REG_TCAM("Tcam key22", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_E_ACL_KEY,   2,  DRV_FTM_TCAM_KEY22, 2*1024, 0x16000000,  0, 0, 3);
    DRV_MEM_REG_TCAM("Tcam key23", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_E_ACL_KEY,   3,  DRV_FTM_TCAM_KEY23, 2*1024, 0x17000000,  0, 0, 3);
    DRV_MEM_REG_TCAM("Tcam key24", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_E_SCL_KEY,   0,  DRV_FTM_TCAM_KEY24, 256,    0x18000000,  0, 0, 4);
    DRV_MEM_REG_TCAM("Tcam key25", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_E_SCL_KEY,   1,  DRV_FTM_TCAM_KEY25, 256,    0x19000000,  0, 0, 4);

    DRV_MEM_REG("Tcam AD0",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  0,   DRV_FTM_TCAM_AD0,   512,   TABLE_INFO(lchip, DsUserIdHash0TcamAdMem_t).addrs[0], 0, 0, 8);
    DRV_MEM_REG("Tcam AD1",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  1,   DRV_FTM_TCAM_AD1,   512,   TABLE_INFO(lchip, DsUserIdHash1TcamAdMem_t).addrs[0], 0, 0, 8);
    DRV_MEM_REG("Tcam AD2",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  2,   DRV_FTM_TCAM_AD2,   1024,  TABLE_INFO(lchip, DsUserIdTcam0AdMem_t).addrs[0],     0, 0, 8);
    DRV_MEM_REG("Tcam AD3",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  3,   DRV_FTM_TCAM_AD3,   1024,  TABLE_INFO(lchip, DsUserIdTcam1AdMem_t).addrs[0],     0, 0, 8);
    DRV_MEM_REG("Tcam AD4",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  4,   DRV_FTM_TCAM_AD4,   2048,  IgrAclTcamAdBlockBase(0), 0, 0, 8);
    DRV_MEM_REG("Tcam AD5",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  5,   DRV_FTM_TCAM_AD5,   2048,  IgrAclTcamAdBlockBase(1), 0, 0, 8);
    DRV_MEM_REG("Tcam AD6",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  6,   DRV_FTM_TCAM_AD6,   2048,  IgrAclTcamAdBlockBase(2), 0, 0, 8);
    DRV_MEM_REG("Tcam AD7",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  7,   DRV_FTM_TCAM_AD7,   2048,  IgrAclTcamAdBlockBase(3), 0, 0, 8);
    DRV_MEM_REG("Tcam AD8",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  8,   DRV_FTM_TCAM_AD8,   2048,  IgrAclTcamAdBlockBase(4), 0, 0, 8);
    DRV_MEM_REG("Tcam AD9",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  9,   DRV_FTM_TCAM_AD9,   2048,  IgrAclTcamAdBlockBase(5), 0, 0, 8);
    DRV_MEM_REG("Tcam AD10",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  10,  DRV_FTM_TCAM_AD10,  2048,  IgrAclTcamAdBlockBase(6), 0, 0, 8);
    DRV_MEM_REG("Tcam AD11",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  11,  DRV_FTM_TCAM_AD11,  2048,  IgrAclTcamAdBlockBase(7), 0, 0, 8);
    DRV_MEM_REG("Tcam AD12",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  12,  DRV_FTM_TCAM_AD12,  2048,  IgrAclTcamAdBlockBase(8), 0, 0, 8);
    DRV_MEM_REG("Tcam AD13",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  13,  DRV_FTM_TCAM_AD13,  2048,  IgrAclTcamAdBlockBase(9), 0, 0, 8);
    DRV_MEM_REG("Tcam AD14",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  14,  DRV_FTM_TCAM_AD14,  2048,  IgrAclTcamAdBlockBase(10), 0, 0, 8);
    DRV_MEM_REG("Tcam AD15",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  15,  DRV_FTM_TCAM_AD15,  2048,  IgrAclTcamAdBlockBase(11), 0, 0, 8);
    DRV_MEM_REG("Tcam AD16",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  16,  DRV_FTM_TCAM_AD16,  2048,  IgrAclTcamAdBlockBase(12), 0, 0, 8);
    DRV_MEM_REG("Tcam AD17",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  17,  DRV_FTM_TCAM_AD17,  2048,  IgrAclTcamAdBlockBase(13), 0, 0, 8);
    DRV_MEM_REG("Tcam AD18",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  18,  DRV_FTM_TCAM_AD18,  2048,  IgrAclTcamAdBlockBase(14), 0, 0, 8);
    DRV_MEM_REG("Tcam AD19",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  19,  DRV_FTM_TCAM_AD19,  2048,  IgrAclTcamAdBlockBase(15), 0, 0, 8);
    DRV_MEM_REG("Tcam AD20",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  20,  DRV_FTM_TCAM_AD20,  1024,  EgrAclTcamAdBlockBase(0), 0, 0, 5);
    DRV_MEM_REG("Tcam AD21",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  21,  DRV_FTM_TCAM_AD21,  1024,  EgrAclTcamAdBlockBase(1), 0, 0, 5);
    DRV_MEM_REG("Tcam AD22",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  22,  DRV_FTM_TCAM_AD22,  1024,  EgrAclTcamAdBlockBase(2), 0, 0, 5);
    DRV_MEM_REG("Tcam AD23",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  23,  DRV_FTM_TCAM_AD23,  1024,  EgrAclTcamAdBlockBase(3), 0, 0, 5);
    DRV_MEM_REG("Tcam AD24",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  24,  DRV_FTM_TCAM_AD24,    256,   TABLE_INFO(lchip, DsEgressScl0TcamAd_t).addrs[0], 0, 0, 3);
    DRV_MEM_REG("Tcam AD25",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  25,  DRV_FTM_TCAM_AD25,    256,   TABLE_INFO(lchip, DsEgressScl1TcamAd_t).addrs[0], 0, 0, 3);

    DRV_MEM_REG_TCAM("LPM key0" ,  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_LPM_KEY,  0,  DRV_FTM_LPM_TCAM_KEY0, 4*1024, 0x20000000, 0, 0, 5);
    DRV_MEM_REG_TCAM("LPM key1" ,  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_LPM_KEY,  1,  DRV_FTM_LPM_TCAM_KEY1, 4*1024, 0x21000000, 0, 0, 5);
    DRV_MEM_REG_TCAM("LPM key2" ,  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_LPM_KEY,  2,  DRV_FTM_LPM_TCAM_KEY2, 4*1024, 0x22000000, 0, 0, 5);
    DRV_MEM_REG_TCAM("LPM key3" ,  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_LPM_KEY,  3,  DRV_FTM_LPM_TCAM_KEY3, 4*1024, 0x23000000, 0, 0, 5);
    DRV_MEM_REG_TCAM("LPM key4" ,  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_LPM_KEY,  4,  DRV_FTM_LPM_TCAM_KEY4, 8*1024, 0x24000000, 0, 0, 5);
    DRV_MEM_REG_TCAM("LPM key5" ,  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_LPM_KEY,  5,  DRV_FTM_LPM_TCAM_KEY5, 8*1024, 0x25000000, 0, 0, 5);

    DRV_MEM_REG("LPM Ad0"  ,  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_LPM_AD,  0,  DRV_FTM_LPM_TCAM_AD0,  4*1024, DRV_LPM_TCAM_AD0_BASE(0), 0, 0, 2);
    DRV_MEM_REG("LPM Ad1"  ,  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_LPM_AD,  1,  DRV_FTM_LPM_TCAM_AD1,  4*1024, DRV_LPM_TCAM_AD0_BASE(1), 0, 0, 2);
    DRV_MEM_REG("LPM Ad2"  ,  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_LPM_AD,  2,  DRV_FTM_LPM_TCAM_AD2,  4*1024, DRV_LPM_TCAM_AD0_BASE(4), 0, 0, 2);
    DRV_MEM_REG("LPM Ad3"  ,  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_LPM_AD,  3,  DRV_FTM_LPM_TCAM_AD3,  4*1024, DRV_LPM_TCAM_AD0_BASE(5), 0, 0, 2);
    DRV_MEM_REG("LPM Ad4"  ,  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_LPM_AD,  4,  DRV_FTM_LPM_TCAM_AD4,  8*1024, DRV_LPM_TCAM_AD1_BASE(0), 0, 0, 2);
    DRV_MEM_REG("LPM Ad5"  ,  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_LPM_AD,  5,  DRV_FTM_LPM_TCAM_AD5,  8*1024, DRV_LPM_TCAM_AD1_BASE(1), 0, 0, 2);

    DRV_MEM_REG_TCAM("Cid Tcam",   DRV_FTM_MEM_TCAM, DRV_FTM_MEM_TCAM_CID_KEY,  0,  DRV_FTM_CID_TCAM,      TABLE_MAX_INDEX(lchip, IpeCidTcamMem_t),             0x30000000, 0, 0, 6);
    DRV_MEM_REG_TCAM("Ltid Tcam",  DRV_FTM_MEM_TCAM, DRV_FTM_MEM_LTID,          0,  DRV_FTM_SEL_TCAM,      TABLE_MAX_INDEX(lchip, DsLtidSelectTcamMem_t),       0x31000000, 0, 0, 7);
    DRV_MEM_REG_TCAM("Vmac Tcam",  DRV_FTM_MEM_TCAM, DRV_FTM_MEM_RT_MAC,        0,  DRV_FTM_RMAC_TCAM,     TABLE_MAX_INDEX(lchip, IpeHdrAdjRouterMacTcamMem_t), 0x32000000, 0, 0, 8);
    DRV_MEM_REG_TCAM("Udf Tcam",   DRV_FTM_MEM_TCAM, DRV_FTM_MEM_UDF,           0,  DRV_FTM_UDF_TCAM,      TABLE_MAX_INDEX(lchip, IpeHdrAdjUdfTcamMem_t),       0x33000000, 0, 0, 9);
    _drv_tmm_mem_cutdown(lchip);
    return 0;
}
#else
int32
drv_mem_init_tmm(uint8 lchip)
{
    DRV_MEM_REG("KeySram0",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  0,   DRV_FTM_SRAM0, 4*4*1024,  DynamicFibKeyShareRamBlockBase(0), 0, 0, 12);
    DRV_MEM_REG("KeySram1",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  1,   DRV_FTM_SRAM1, 4*4*1024,  DynamicFibKeyShareRamBlockBase(1), 0, 0, 12);
    DRV_MEM_REG("KeySram2",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  2,   DRV_FTM_SRAM2, 4*16*1024, DynamicFibKeyShareRamBlockBase(2), 0, 0, 12);
    DRV_MEM_REG("KeySram3",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  3,   DRV_FTM_SRAM3, 4*16*1024, DynamicFibKeyShareRamBlockBase(3), 0, 0, 12);
    DRV_MEM_REG("KeySram4",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  4,   DRV_FTM_SRAM4, 4*16*1024, DynamicFibKeyShareRamBlockBase(4), 0, 0, 12);
    DRV_MEM_REG("KeySram5",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  5,   DRV_FTM_SRAM5, 4*16*1024, DynamicFibKeyShareRamBlockBase(5), DynamicFibKeyAntFlowBlockBase(0), 0, 12);
    DRV_MEM_REG("KeySram6",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  6,   DRV_FTM_SRAM6, 4*16*1024, DynamicFibKeyShareRamBlockBase(6), DynamicFibKeyAntFlowBlockBase(1), 0, 12);
    DRV_MEM_REG("KeySram7",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  7,   DRV_FTM_SRAM7, 4*2*1024,  DynamicFibKeyShareRamBlockBase(7), 0, 0, 12);
    DRV_MEM_REG("KeySram8",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  8,   DRV_FTM_SRAM8, 4*2*1024,  DynamicFibKeyShareRamBlockBase(8), 0, 0, 12);

    DRV_MEM_REG("KeySram9",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  9,   DRV_FTM_SRAM9,  4*2*1024, DynamicMiscKeyShareRamBlockBase(0),  DynamicMiscKeyMplsHashBlockBase(0), 0, 12);
    DRV_MEM_REG("KeySram10",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  10,  DRV_FTM_SRAM10, 4*2*1024, DynamicMiscKeyShareRamBlockBase(1),  DynamicMiscKeyMplsHashBlockBase(1), 0, 12);
    DRV_MEM_REG("KeySram11",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  11,  DRV_FTM_SRAM11, 4*4*1024, DynamicMiscKeyShareRamBlockBase(2),  0, 0, 12);
    DRV_MEM_REG("KeySram12",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  12,  DRV_FTM_SRAM12, 4*4*1024, DynamicMiscKeyShareRamBlockBase(3),  0, 0, 12);
    DRV_MEM_REG("KeySram13",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  13,  DRV_FTM_SRAM13, 4*2*1024, DynamicMiscKeyShareRamBlockBase(4),  0, 0, 12);
    DRV_MEM_REG("KeySram14",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  14,  DRV_FTM_SRAM14, 4*2*1024, DynamicMiscKeyShareRamBlockBase(5),  0, 0, 12);
    DRV_MEM_REG("KeySram15",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  15,  DRV_FTM_SRAM15, 4*2*1024, DynamicMiscKeyShareRamBlockBase(6),  0, 0, 12);
    DRV_MEM_REG("KeySram16",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  16,  DRV_FTM_SRAM16, 4*2*1024, DynamicMiscKeyShareRamBlockBase(7),  0, 0, 12);
    DRV_MEM_REG("KeySram17",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  17,  DRV_FTM_SRAM17, 4*2*1024, DynamicMiscKeyShareRamBlockBase(8),  0, 0, 12);
    DRV_MEM_REG("KeySram18",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  18,  DRV_FTM_SRAM18, 4*2*1024, DynamicMiscKeyShareRamBlockBase(9),  0, 0, 12);
    DRV_MEM_REG("KeySram19",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_KEY,  19,  DRV_FTM_SRAM19, 4*2*1024, DynamicMiscKeyShareRamBlockBase(10), 0, 0, 12);

    DRV_MEM_REG("AdSram0",    DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_AD,  0,    DRV_FTM_SRAM20, 4*16*1024, DynamicAdShareRamBlockBase(0), 0, 0, 16);
    DRV_MEM_REG("AdSram1",    DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_AD,  1,    DRV_FTM_SRAM21, 4*8*1024,  DynamicAdShareRamBlockBase(1), 0, 0, 16);
    DRV_MEM_REG("AdSram2",    DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_AD,  2,    DRV_FTM_SRAM22, 4*8*1024,  DynamicAdShareRamBlockBase(2), 0, 0, 16);
    DRV_MEM_REG("AdSram3",    DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_AD,  3,    DRV_FTM_SRAM23, 4*4*1024,  DynamicAdShareRamBlockBase(3), 0, 0, 16);
    DRV_MEM_REG("AdSram4",    DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_AD,  4,    DRV_FTM_SRAM24, 4*4*1024,  DynamicAdShareRamBlockBase(4), DynamicAdGemPortBlockBase(4), 0, 16);
    DRV_MEM_REG("AdSram5",    DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_AD,  5,    DRV_FTM_SRAM25, 4*2*1024,  DynamicAdShareRamBlockBase(5), DynamicAdGemPortBlockBase(5), 0, 16);
    DRV_MEM_REG("AdSram6",    DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_AD,  6,    DRV_FTM_SRAM26, 4*2*1024,  DynamicAdShareRamBlockBase(6), DynamicAdGemPortBlockBase(6), 0, 16);

    DRV_MEM_REG("EditSram0",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_EDIT,  0,  DRV_FTM_SRAM27, 4*16*1024, DynamicEditShareRamBlockBase(0), 0, 0, 16);
    DRV_MEM_REG("EditSram1",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_EDIT,  1,  DRV_FTM_SRAM28, 4*8*1024,  DynamicEditShareRamBlockBase(1), 0, 0, 16);
    DRV_MEM_REG("EditSram2",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_EDIT,  2,  DRV_FTM_SRAM29, 4*4*1024,  DynamicEditShareRamBlockBase(2), 0, 0, 16);
    DRV_MEM_REG("EditSram3",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_EDIT,  3,  DRV_FTM_SRAM30, 4*4*1024,  DynamicEditShareRamBlockBase(3), 0, 0, 16);
    DRV_MEM_REG("EditSram4",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_EDIT,  4,  DRV_FTM_SRAM31, 4*2*1024,  DynamicEditShareRamBlockBase(4), 0, 0, 16);
    DRV_MEM_REG("EditSram5",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_EDIT,  5,  DRV_FTM_SRAM32, 4*2*1024,  DynamicEditShareRamBlockBase(5), 0, 0, 16);

    DRV_MEM_REG("OamSram0",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_OAM,  0,   DRV_FTM_SRAM33, 4*256,     TABLE_INFO(lchip, DsRmepHashKeyTable0_t).addrs[0], 0, 0, 8);
    DRV_MEM_REG("OamSram1",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_OAM,  1,   DRV_FTM_SRAM34, 4*256,     TABLE_INFO(lchip, DsRmepHashKeyTable1_t).addrs[0], 0, 0, 8);
    DRV_MEM_REG("OamSram2",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_OAM,  2,   DRV_FTM_SRAM35, 8*2*1024,  TABLE_INFO(lchip, DsMp_t).addrs[0],                0, 0, 6);
    DRV_MEM_REG("OamSram3",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_OAM,  3,   DRV_FTM_SRAM36, 4*1*1024,  TABLE_INFO(lchip, DsMa_t).addrs[0],                0, 0, 3);
    DRV_MEM_REG("OamSram4",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_OAM,  4,   DRV_FTM_SRAM37, 4*1024,  TABLE_INFO(lchip, DsMaName_t).addrs[0],            0, 0, 4);
    DRV_MEM_REG("OamSram5",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_OAM,  5,   DRV_FTM_SRAM38, 4*1*1024,  TABLE_INFO(lchip, DsOamHashKeyTable0_t).addrs[0],  0, 0, 12);
    DRV_MEM_REG("OamSram6",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_OAM,  6,   DRV_FTM_SRAM39, 4*1*1024,  TABLE_INFO(lchip, DsOamHashKeyTable1_t).addrs[0],  0, 0, 12);

    DRV_MEM_REG("QueSram0",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_QUEUE,  0,  DRV_FTM_SRAM40, 4096,      QueueHashRamBlockBase(0), 0, 0, 4);
    DRV_MEM_REG("QueSram1",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_QUEUE,  1,  DRV_FTM_SRAM41, 4096,      QueueHashRamBlockBase(1), 0, 0, 4);
    DRV_MEM_REG("QueSram2",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_QUEUE,  2,  DRV_FTM_SRAM42, 4096,      QueueHashRamBlockBase(2), 0, 0, 4);

    DRV_MEM_REG("IpfixKey",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_IPFIX,  0,  DRV_FTM_SRAM43, 256*1024,  TABLE_INFO(lchip, DsIpfixHashKeyTable12W_t).addrs[0],  0, 0, 16);
    DRV_MEM_REG("IpfixAd0",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_IPFIX,  1,  DRV_FTM_SRAM44, 256*1024,  TABLE_INFO(lchip, DsIpfixSessionRecordMem0_t).addrs[0], 0, 0, 8);
    DRV_MEM_REG("IpfixAd1",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_DYNAMIC_IPFIX,  2,  DRV_FTM_SRAM45, 256*1024,  TABLE_INFO(lchip, DsIpfixSessionRecordMem1_t).addrs[0], 0, 0, 8);

    DRV_MEM_REG_TCAM("Tcam key0",  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_SCL0_KEY,  0,  DRV_FTM_TCAM_KEY0,  512,    IgrSclTcam0KeyBlockBase(0), 0, 0, 0);
    DRV_MEM_REG_TCAM("Tcam key1",  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_SCL0_KEY,  1,  DRV_FTM_TCAM_KEY1,  512,    IgrSclTcam0KeyBlockBase(1), 0, 0, 0);
    DRV_MEM_REG_TCAM("Tcam key2",  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_SCL1_KEY,  0,  DRV_FTM_TCAM_KEY2,  2*1024, IgrSclTcam1KeyBlockBase(0), 0, 0, 1);
    DRV_MEM_REG_TCAM("Tcam key3",  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_SCL1_KEY,  1,  DRV_FTM_TCAM_KEY3,  2*1024, IgrSclTcam1KeyBlockBase(1), 0, 0, 1);
    DRV_MEM_REG_TCAM("Tcam key4",  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   0,  DRV_FTM_TCAM_KEY4,  2*2048, IgrAclTcamKeyBlockBase(0),  0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key5",  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   1,  DRV_FTM_TCAM_KEY5,  2*2048, IgrAclTcamKeyBlockBase(1),  0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key6",  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   2,  DRV_FTM_TCAM_KEY6,  2*2048, IgrAclTcamKeyBlockBase(2),  0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key7",  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   3,  DRV_FTM_TCAM_KEY7,  2*2048, IgrAclTcamKeyBlockBase(3),  0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key8",  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   4,  DRV_FTM_TCAM_KEY8,  2*2048, IgrAclTcamKeyBlockBase(4),  0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key9",  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   5,  DRV_FTM_TCAM_KEY9,  2*2048, IgrAclTcamKeyBlockBase(5),  0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key10", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   6,  DRV_FTM_TCAM_KEY10, 2*2048, IgrAclTcamKeyBlockBase(6),  0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key11", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   7,  DRV_FTM_TCAM_KEY11, 2*2048, IgrAclTcamKeyBlockBase(7),  0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key12", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   8,  DRV_FTM_TCAM_KEY12, 2*2048, IgrAclTcamKeyBlockBase(8),  0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key13", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   9,  DRV_FTM_TCAM_KEY13, 2*2048, IgrAclTcamKeyBlockBase(9),  0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key14", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   10, DRV_FTM_TCAM_KEY14, 2*2048, IgrAclTcamKeyBlockBase(10), 0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key15", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   11, DRV_FTM_TCAM_KEY15, 2*2048, IgrAclTcamKeyBlockBase(11), 0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key16", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   12, DRV_FTM_TCAM_KEY16, 2*2048, IgrAclTcamKeyBlockBase(12), 0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key17", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   13, DRV_FTM_TCAM_KEY17, 2*2048, IgrAclTcamKeyBlockBase(13), 0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key18", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   14, DRV_FTM_TCAM_KEY18, 2*2048, IgrAclTcamKeyBlockBase(14), 0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key19", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_I_ACL_KEY,   15, DRV_FTM_TCAM_KEY19, 2*2048, IgrAclTcamKeyBlockBase(15), 0, 0, 2);
    DRV_MEM_REG_TCAM("Tcam key20", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_E_ACL_KEY,   0,  DRV_FTM_TCAM_KEY20, 2*1024, EgrAclTcamKeyBlockBase(0),  0, 0, 3);
    DRV_MEM_REG_TCAM("Tcam key21", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_E_ACL_KEY,   1,  DRV_FTM_TCAM_KEY21, 2*1024, EgrAclTcamKeyBlockBase(1),  0, 0, 3);
    DRV_MEM_REG_TCAM("Tcam key22", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_E_ACL_KEY,   2,  DRV_FTM_TCAM_KEY22, 2*1024, EgrAclTcamKeyBlockBase(2),  0, 0, 3);
    DRV_MEM_REG_TCAM("Tcam key23", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_E_ACL_KEY,   3,  DRV_FTM_TCAM_KEY23, 2*1024, EgrAclTcamKeyBlockBase(3),  0, 0, 3);
    DRV_MEM_REG_TCAM("Tcam key24", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_E_SCL_KEY,   0,  DRV_FTM_TCAM_KEY24, 256,    EgrSclTcamKeyBlockBase(0),  0, 0, 4);
    DRV_MEM_REG_TCAM("Tcam key25", DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_E_SCL_KEY,   1,  DRV_FTM_TCAM_KEY25, 256,    EgrSclTcamKeyBlockBase(1),  0, 0, 4);

    DRV_MEM_REG("Tcam AD0",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  0,   DRV_FTM_TCAM_AD0,   512,   TABLE_INFO(lchip, DsUserIdHash0TcamAdMem_t).addrs[0], 0, 0, 8);
    DRV_MEM_REG("Tcam AD1",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  1,   DRV_FTM_TCAM_AD1,   512,   TABLE_INFO(lchip, DsUserIdHash1TcamAdMem_t).addrs[0], 0, 0, 8);
    DRV_MEM_REG("Tcam AD2",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  2,   DRV_FTM_TCAM_AD2,   1024,  TABLE_INFO(lchip, DsUserIdTcam0AdMem_t).addrs[0],     0, 0, 8);
    DRV_MEM_REG("Tcam AD3",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  3,   DRV_FTM_TCAM_AD3,   1024,  TABLE_INFO(lchip, DsUserIdTcam1AdMem_t).addrs[0],     0, 0, 8);
    DRV_MEM_REG("Tcam AD4",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  4,   DRV_FTM_TCAM_AD4,   2048,  IgrAclTcamAdBlockBase(0), 0, 0, 8);
    DRV_MEM_REG("Tcam AD5",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  5,   DRV_FTM_TCAM_AD5,   2048,  IgrAclTcamAdBlockBase(1), 0, 0, 8);
    DRV_MEM_REG("Tcam AD6",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  6,   DRV_FTM_TCAM_AD6,   2048,  IgrAclTcamAdBlockBase(2), 0, 0, 8);
    DRV_MEM_REG("Tcam AD7",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  7,   DRV_FTM_TCAM_AD7,   2048,  IgrAclTcamAdBlockBase(3), 0, 0, 8);
    DRV_MEM_REG("Tcam AD8",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  8,   DRV_FTM_TCAM_AD8,   2048,  IgrAclTcamAdBlockBase(4), 0, 0, 8);
    DRV_MEM_REG("Tcam AD9",   DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  9,   DRV_FTM_TCAM_AD9,   2048,  IgrAclTcamAdBlockBase(5), 0, 0, 8);
    DRV_MEM_REG("Tcam AD10",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  10,  DRV_FTM_TCAM_AD10,  2048,  IgrAclTcamAdBlockBase(6), 0, 0, 8);
    DRV_MEM_REG("Tcam AD11",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  11,  DRV_FTM_TCAM_AD11,  2048,  IgrAclTcamAdBlockBase(7), 0, 0, 8);
    DRV_MEM_REG("Tcam AD12",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  12,  DRV_FTM_TCAM_AD12,  2048,  IgrAclTcamAdBlockBase(8), 0, 0, 8);
    DRV_MEM_REG("Tcam AD13",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  13,  DRV_FTM_TCAM_AD13,  2048,  IgrAclTcamAdBlockBase(9), 0, 0, 8);
    DRV_MEM_REG("Tcam AD14",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  14,  DRV_FTM_TCAM_AD14,  2048,  IgrAclTcamAdBlockBase(10), 0, 0, 8);
    DRV_MEM_REG("Tcam AD15",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  15,  DRV_FTM_TCAM_AD15,  2048,  IgrAclTcamAdBlockBase(11), 0, 0, 8);
    DRV_MEM_REG("Tcam AD16",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  16,  DRV_FTM_TCAM_AD16,  2048,  IgrAclTcamAdBlockBase(12), 0, 0, 8);
    DRV_MEM_REG("Tcam AD17",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  17,  DRV_FTM_TCAM_AD17,  2048,  IgrAclTcamAdBlockBase(13), 0, 0, 8);
    DRV_MEM_REG("Tcam AD18",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  18,  DRV_FTM_TCAM_AD18,  2048,  IgrAclTcamAdBlockBase(14), 0, 0, 8);
    DRV_MEM_REG("Tcam AD19",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  19,  DRV_FTM_TCAM_AD19,  2048,  IgrAclTcamAdBlockBase(15), 0, 0, 8);
    DRV_MEM_REG("Tcam AD20",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  20,  DRV_FTM_TCAM_AD20,  1024,  EgrAclTcamAdBlockBase(0), 0, 0, 5);
    DRV_MEM_REG("Tcam AD21",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  21,  DRV_FTM_TCAM_AD21,  1024,  EgrAclTcamAdBlockBase(1), 0, 0, 5);
    DRV_MEM_REG("Tcam AD22",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  22,  DRV_FTM_TCAM_AD22,  1024,  EgrAclTcamAdBlockBase(2), 0, 0, 5);
    DRV_MEM_REG("Tcam AD23",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  23,  DRV_FTM_TCAM_AD23,  1024,  EgrAclTcamAdBlockBase(3), 0, 0, 5);
    DRV_MEM_REG("Tcam AD24",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  24,  DRV_FTM_TCAM_AD24,    256,   TABLE_INFO(lchip, DsEgressScl0TcamAd_t).addrs[0], 0, 0, 3);
    DRV_MEM_REG("Tcam AD25",  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_FLOW_AD,  25,  DRV_FTM_TCAM_AD25,    256,   TABLE_INFO(lchip, DsEgressScl1TcamAd_t).addrs[0], 0, 0, 3);

    #ifdef EMULATION_ENV
    DRV_MEM_REG_TCAM("LPM key0" ,  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_LPM_KEY,  0,  DRV_FTM_LPM_TCAM_KEY0, 32, LpmTcam0KeyBlockBase(0), 0, 0, 5);
    DRV_MEM_REG_TCAM("LPM key1" ,  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_LPM_KEY,  1,  DRV_FTM_LPM_TCAM_KEY1, 32, LpmTcam0KeyBlockBase(1), 0, 0, 5);
    DRV_MEM_REG_TCAM("LPM key2" ,  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_LPM_KEY,  2,  DRV_FTM_LPM_TCAM_KEY2, 32, LpmTcam0KeyBlockBase(2), 0, 0, 5);
    DRV_MEM_REG_TCAM("LPM key3" ,  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_LPM_KEY,  3,  DRV_FTM_LPM_TCAM_KEY3, 32, LpmTcam0KeyBlockBase(3), 0, 0, 5);
    DRV_MEM_REG_TCAM("LPM key4" ,  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_LPM_KEY,  4,  DRV_FTM_LPM_TCAM_KEY4, 32, LpmTcam1KeyBlockBase(0), 0, 0, 5);
    DRV_MEM_REG_TCAM("LPM key5" ,  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_LPM_KEY,  5,  DRV_FTM_LPM_TCAM_KEY5, 32, LpmTcam1KeyBlockBase(1), 0, 0, 5);

    DRV_MEM_REG("LPM Ad0"  ,  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_LPM_AD,  0,  DRV_FTM_LPM_TCAM_AD0,  32, DRV_LPM_TCAM_AD0_BASE(0), 0, 0, 2);
    DRV_MEM_REG("LPM Ad1"  ,  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_LPM_AD,  1,  DRV_FTM_LPM_TCAM_AD1,  32, DRV_LPM_TCAM_AD0_BASE(1), 0, 0, 2);
    DRV_MEM_REG("LPM Ad2"  ,  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_LPM_AD,  2,  DRV_FTM_LPM_TCAM_AD2,  32, DRV_LPM_TCAM_AD0_BASE(4), 0, 0, 2);
    DRV_MEM_REG("LPM Ad3"  ,  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_LPM_AD,  3,  DRV_FTM_LPM_TCAM_AD3,  32, DRV_LPM_TCAM_AD0_BASE(5), 0, 0, 2);
    DRV_MEM_REG("LPM Ad4"  ,  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_LPM_AD,  4,  DRV_FTM_LPM_TCAM_AD4,  32, DRV_LPM_TCAM_AD1_BASE(0), 0, 0, 2);
    DRV_MEM_REG("LPM Ad5"  ,  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_LPM_AD,  5,  DRV_FTM_LPM_TCAM_AD5,  32, DRV_LPM_TCAM_AD1_BASE(1), 0, 0, 2);
    #else
    DRV_MEM_REG_TCAM("LPM key0" ,  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_LPM_KEY,  0,  DRV_FTM_LPM_TCAM_KEY0, 4*1024, LpmTcam0KeyBlockBase(0), 0, 0, 5);
    DRV_MEM_REG_TCAM("LPM key1" ,  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_LPM_KEY,  1,  DRV_FTM_LPM_TCAM_KEY1, 4*1024, LpmTcam0KeyBlockBase(1), 0, 0, 5);
    DRV_MEM_REG_TCAM("LPM key2" ,  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_LPM_KEY,  2,  DRV_FTM_LPM_TCAM_KEY2, 4*1024, LpmTcam0KeyBlockBase(4), 0, 0, 5);
    DRV_MEM_REG_TCAM("LPM key3" ,  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_LPM_KEY,  3,  DRV_FTM_LPM_TCAM_KEY3, 4*1024, LpmTcam0KeyBlockBase(5), 0, 0, 5);
    DRV_MEM_REG_TCAM("LPM key4" ,  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_LPM_KEY,  4,  DRV_FTM_LPM_TCAM_KEY4, 8*1024, LpmTcam1KeyBlockBase(0), 0, 0, 5);
    DRV_MEM_REG_TCAM("LPM key5" ,  DRV_FTM_MEM_TCAM,   DRV_FTM_MEM_TCAM_LPM_KEY,  5,  DRV_FTM_LPM_TCAM_KEY5, 8*1024, LpmTcam1KeyBlockBase(1), 0, 0, 5);

    DRV_MEM_REG("LPM Ad0"  ,  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_LPM_AD,  0,  DRV_FTM_LPM_TCAM_AD0,  4*1024, DRV_LPM_TCAM_AD0_BASE(0), 0, 0, 2);
    DRV_MEM_REG("LPM Ad1"  ,  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_LPM_AD,  1,  DRV_FTM_LPM_TCAM_AD1,  4*1024, DRV_LPM_TCAM_AD0_BASE(1), 0, 0, 2);
    DRV_MEM_REG("LPM Ad2"  ,  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_LPM_AD,  2,  DRV_FTM_LPM_TCAM_AD2,  4*1024, DRV_LPM_TCAM_AD0_BASE(4), 0, 0, 2);
    DRV_MEM_REG("LPM Ad3"  ,  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_LPM_AD,  3,  DRV_FTM_LPM_TCAM_AD3,  4*1024, DRV_LPM_TCAM_AD0_BASE(5), 0, 0, 2);
    DRV_MEM_REG("LPM Ad4"  ,  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_LPM_AD,  4,  DRV_FTM_LPM_TCAM_AD4,  8*1024, DRV_LPM_TCAM_AD1_BASE(0), 0, 0, 2);
    DRV_MEM_REG("LPM Ad5"  ,  DRV_FTM_MEM_DYNAMIC,   DRV_FTM_MEM_TCAM_LPM_AD,  5,  DRV_FTM_LPM_TCAM_AD5,  8*1024, DRV_LPM_TCAM_AD1_BASE(1), 0, 0, 2);
    #endif

    DRV_MEM_REG_TCAM("Cid Tcam",   DRV_FTM_MEM_TCAM, DRV_FTM_MEM_TCAM_CID_KEY,  0,  DRV_FTM_CID_TCAM,      TABLE_MAX_INDEX(lchip, IpeCidTcamMem_t),             TABLE_INFO(lchip, IpeCidTcamMem_t).addrs[0],             0, 0, 6);
    DRV_MEM_REG_TCAM("Ltid Tcam",  DRV_FTM_MEM_TCAM, DRV_FTM_MEM_LTID,          0,  DRV_FTM_SEL_TCAM,      TABLE_MAX_INDEX(lchip, DsLtidSelectTcamMem_t),       TABLE_INFO(lchip, DsLtidSelectTcamMem_t).addrs[0],       0, 0, 7);
    DRV_MEM_REG_TCAM("Vmac Tcam",  DRV_FTM_MEM_TCAM, DRV_FTM_MEM_RT_MAC,        0,  DRV_FTM_RMAC_TCAM,     TABLE_MAX_INDEX(lchip, IpeHdrAdjRouterMacTcamMem_t), TABLE_INFO(lchip, IpeHdrAdjRouterMacTcamMem_t).addrs[0], 0, 0, 8);
    DRV_MEM_REG_TCAM("Udf Tcam",   DRV_FTM_MEM_TCAM, DRV_FTM_MEM_UDF,           0,  DRV_FTM_UDF_TCAM,      TABLE_MAX_INDEX(lchip, IpeHdrAdjUdfTcamMem_t),       TABLE_INFO(lchip, IpeHdrAdjUdfTcamMem_t).addrs[0],       0, 0, 9);

    return 0;
}
#endif



int32
drv_enum_init_tmm(uint8 lchip)
{
    DRV_CONST(DRV_IPFIX_EXPORTREASON_NO_EXPORT)                  = 0x0;
    DRV_CONST(DRV_IPFIX_EXPORTREASON_EXPIRED)                    = 0x1;
    DRV_CONST(DRV_IPFIX_EXPORTREASON_TCP_SESSION_CLOSE)          = 0x2;
    DRV_CONST(DRV_IPFIX_EXPORTREASON_PACKET_COUNT_OVERFLOW)      = 0x3;
    DRV_CONST(DRV_IPFIX_EXPORTREASON_DROP_PKT_COUNT_OVERFLOW)    = 0x4;
    DRV_CONST(DRV_IPFIX_EXPORTREASON_NEW_FLOW_EXPORT)            = 0x5;
    DRV_CONST(DRV_IPFIX_EXPORTREASON_PACKET_DISCARDTYPE_CHANGE)  = 0x6;
    DRV_CONST(DRV_IPFIX_EXPORTREASON_TS_COUNT_OVERFLOW)          = 0x7;
    DRV_CONST(DRV_IPFIX_EXPORTREASON_JITTER_OVERFLOW)            = 0x8;
    DRV_CONST(DRV_IPFIX_EXPORTREASON_LATENCY_OVERFLOW)           = 0x9;
    DRV_CONST(DRV_IPFIX_EXPORTREASON_TTL_CHANGE)                 = 0xa;
    DRV_CONST(DRV_IPFIX_EXPORTREASON_BYTE_COUNT_OVERFLOW)        = 0xb;
    DRV_CONST(DRV_IPFIX_EXPORTREASON_DESTINATION_CHANGE)         = 0xc;
    DRV_CONST(DRV_IPFIX_EXPORTREASON_FLUSH_TIMER_EXPORT)         = 0xd;
    DRV_CONST(DRV_IPFIX_EXPORTREASON_SESSION_PACKET_DROP)        = 0xe;
    DRV_CONST(DRV_IPFIX_EXPORTREASON_RTP_SEQID_DISORDER)         = 0xf;

    DRV_CONST(DRV_DS_CATEGORY_ID_PAIR_TCAM_LOOKUP_KEY_BYTES) = 8;
    DRV_CONST(DRV_TCAMKEYTYPE_MACKEY_160)           = 0x0;
    DRV_CONST(DRV_TCAMKEYTYPE_L3KEY_160)            = 0x1;
    DRV_CONST(DRV_TCAMKEYTYPE_L3KEY_320)            = 0x2;
    DRV_CONST(DRV_TCAMKEYTYPE_IPV6KEY_320)          = 0x3;
    DRV_CONST(DRV_TCAMKEYTYPE_IPV6KEY_640)          = 0x4;
    DRV_CONST(DRV_TCAMKEYTYPE_MACL3KEY_320)         = 0x6;
    DRV_CONST(DRV_TCAMKEYTYPE_MACL3KEY_640)         = 0xe;
    DRV_CONST(DRV_TCAMKEYTYPE_MACIPV6KEY_640)       = 0x7;
    DRV_CONST(DRV_TCAMKEYTYPE_CIDKEY_160)           = 0x8;
    DRV_CONST(DRV_TCAMKEYTYPE_SHORTKEY_80)          = 0x9;
    DRV_CONST(DRV_TCAMKEYTYPE_FORWARDKEY_320)       = 0xa;
    DRV_CONST(DRV_TCAMKEYTYPE_FORWARDKEY_640)       = 0xb;
    DRV_CONST(DRV_TCAMKEYTYPE_COPPKEY_320)          = 0xc;
    DRV_CONST(DRV_TCAMKEYTYPE_COPPKEY_640)          = 0xd;
    DRV_CONST(DRV_TCAMKEYTYPE_UDFKEY_320)           = 0x5;
    DRV_CONST(DRV_XC_OAM_HASH_CAM_NUM)      = 0;




    DRV_CONST(DRV_SCL_KEY_TYPE_MACKEY160)           = 0xb;
    DRV_CONST(DRV_SCL_KEY_TYPE_MACL3KEY320)         = 0x3;
    DRV_CONST(DRV_SCL_KEY_TYPE_L3KEY160)            = 0x1;
    DRV_CONST(DRV_SCL_KEY_TYPE_IPV6KEY320)          = 0x2;
    DRV_CONST(DRV_SCL_KEY_TYPE_MACIPV6KEY640)       = 0x7;
    DRV_CONST(DRV_SCL_KEY_TYPE_RESOLVE_CONFLICT)    = 0xf;  /* invalid */
    DRV_CONST(DRV_SCL_KEY_TYPE_UDFKEY160)           = 0x6;
    DRV_CONST(DRV_SCL_KEY_TYPE_UDFKEY320)           = 0x4;
    DRV_CONST(DRV_SCL_KEY_TYPE_UDFKEY640)           = 0x5;
    DRV_CONST(DRV_SCL_KEY_TYPE_MASK)                = 0xF;

    DRV_CONST(DRV_UDFPOSTYPE_NONE)                    = 0x0;
    DRV_CONST(DRV_UDFPOSTYPE_OUTER_L2)                = 0x1;
    DRV_CONST(DRV_UDFPOSTYPE_OUTER_L3)                = 0x2;
    DRV_CONST(DRV_UDFPOSTYPE_OUTER_L4)                = 0x3;
    DRV_CONST(DRV_UDFPOSTYPE_INNER_L2)                = 0x4;
    DRV_CONST(DRV_UDFPOSTYPE_INNER_L3)                = 0x5;
    DRV_CONST(DRV_UDFPOSTYPE_INNER_L4)                = 0x6;

    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_DISABLE )             = 0x0;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_DOUBLEVLANPORT)       = 0x1;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_SVLANPORT)            = 0x2;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_CVLANPORT)            = 0x3;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_SVLANCOSPORT)         = 0x4;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_CVLANCOSPORT)         = 0x5;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_PORTVLANCROSS)        = 0x6;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_PORTCROSS)            = 0x7;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_PORT)                 = 0x8;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_SVLANPORTMAC)         = 0x9;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_TUNNELPBB)            = 0xa;
    DRV_CONST(DRV_EGRESSSCLHASHTYPE_FIDDVPGROUP)            = 0xb;
    DRV_CONST(DRV_EGRESSSCLHASHTYPE_METADATADVPGROUP)       = 0xd;
    DRV_CONST(DRV_EGRESSSCLHASHTYPE_VPPAIR)                 = 0xc;
    DRV_CONST(DRV_EGRESSSCLHASHTYPE_I2ECIDDVPGROUP)         = 0xe;

    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_ETH)                  = 0x1;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_BFD)                  = 0x2;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_MPLSLABEL)            = 0x3;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_MPLSSECTION)          = 0x4;
    DRV_CONST(DRV_EGRESSXCOAMHASHTYPE_RMEP)                 = 0x14;

    DRV_CONST(DRV_FIBHOST0PRIMARYHASHTYPE_FCOE)             = 0x0;
    DRV_CONST(DRV_FIBHOST0PRIMARYHASHTYPE_IPV4)             = 0x1;
    DRV_CONST(DRV_FIBHOST0PRIMARYHASHTYPE_IPV6MCAST)        = 0x2;
    DRV_CONST(DRV_FIBHOST0PRIMARYHASHTYPE_IPV6UCAST)        = 0x3;
    DRV_CONST(DRV_FIBHOST0PRIMARYHASHTYPE_MAC)              = 0x4;
    DRV_CONST(DRV_FIBHOST0PRIMARYHASHTYPE_MACIPV6MCAST)     = 0x5;
    DRV_CONST(DRV_FIBHOST0PRIMARYHASHTYPE_TRILL)            = 0x6;
    DRV_CONST(DRV_FIBHOST0PRIMARYHASHTYPE_MACIPV4MCAST)     = 0x7;

    DRV_CONST(DRV_FIBHOST1PRIMARYHASHTYPE_IPV4)             = 0x0;
    DRV_CONST(DRV_FIBHOST1PRIMARYHASHTYPE_IPV6NATDA)        = 0x1;
    DRV_CONST(DRV_FIBHOST1PRIMARYHASHTYPE_IPV6NATSA)        = 0x2;
    DRV_CONST(DRV_FIBHOST1PRIMARYHASHTYPE_OTHER)            = 0x3;

    DRV_CONST(DRV_FLOWHASHTYPE_INVALID)                     = 0x0;
    DRV_CONST(DRV_FLOWHASHTYPE_L2)                          = 0x1;
    DRV_CONST(DRV_FLOWHASHTYPE_L2L3)                        = 0x2;
    DRV_CONST(DRV_FLOWHASHTYPE_L3IPV4)                      = 0x3;
    DRV_CONST(DRV_FLOWHASHTYPE_L3IPV6)                      = 0x4;
    DRV_CONST(DRV_FLOWHASHTYPE_L3MPLS)                      = 0x5;

    DRV_CONST(DRV_USERIDHASHTYPE_DISABLE)                   = 0x0;
    DRV_CONST(DRV_USERIDHASHTYPE_DOUBLEVLANPORT)            = 0x1;
    DRV_CONST(DRV_USERIDHASHTYPE_SVLANPORT)                 = 0x2;
    DRV_CONST(DRV_USERIDHASHTYPE_CVLANPORT)                 = 0x3;
    DRV_CONST(DRV_USERIDHASHTYPE_SVLANCOSPORT)              = 0x4;
    DRV_CONST(DRV_USERIDHASHTYPE_CVLANCOSPORT)              = 0x5;
    DRV_CONST(DRV_USERIDHASHTYPE_MACPORT)                   = 0x6;
    DRV_CONST(DRV_USERIDHASHTYPE_IPV4PORT)                  = 0x7;
    DRV_CONST(DRV_USERIDHASHTYPE_MAC)                       = 0x8;
    DRV_CONST(DRV_USERIDHASHTYPE_IPV4SA)                    = 0x9;
    DRV_CONST(DRV_USERIDHASHTYPE_PORT)                      = 0xa;
    DRV_CONST(DRV_USERIDHASHTYPE_SVLANMACSA)                = 0xb;
    DRV_CONST(DRV_USERIDHASHTYPE_SVLAN)                     = 0xc;
    DRV_CONST(DRV_USERIDHASHTYPE_ECIDNAMESPACE)             = 0xd;
    DRV_CONST(DRV_USERIDHASHTYPE_INGECIDNAMESPACE)          = 0xe;
    DRV_CONST(DRV_USERIDHASHTYPE_IPV6SA)                    = 0xf;
    DRV_CONST(DRV_USERIDHASHTYPE_IPV6PORT)                  = 0x10;
    DRV_CONST(DRV_USERIDHASHTYPE_IPV4DA)                    = 0x11;
    DRV_CONST(DRV_USERIDHASHTYPE_IPV6DA)                    = 0x12;
    DRV_CONST(DRV_USERIDHASHTYPE_VLANDSCPPORT)                  = 0x13;
    /*DRV_CONST(DRV_USERIDHASHTYPE_CAPWAPSTASTATUS)           = 0x11;*/
    /*DRV_CONST(DRV_USERIDHASHTYPE_CAPWAPSTASTATUSMC)         = 0x12;*/
    /*DRV_CONST(DRV_USERIDHASHTYPE_CAPWAPMACDAFORWARD)        = 0x13;*/
    /*DRV_CONST(DRV_USERIDHASHTYPE_CAPWAPVLANFORWARD)         = 0x14;*/
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4)                = 0x15;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELTYPE_START)         = DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4);
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4GREKEY)          = 0x16;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4UDP)             = 0x17;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELTRILLUCRPF)          = 0x19;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELTRILLUCDECAP)        = 0x1a;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELTRILLMCRPF)          = 0x1b;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELTRILLMCDECAP)        = 0x1c;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELTRILLMCADJ)          = 0x1d;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4RPF)             = 0x1e;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4UCVXLANMODE0)    = 0x1f;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4UCVXLANMODE1)    = 0x20;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6UCVXLANMODE0)    = 0x21;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6UCVXLANMODE1)    = 0x22;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4UCNVGREMODE0)    = 0x23;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4UCNVGREMODE1)    = 0x24;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6UCNVGREMODE0)    = 0x25;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6UCNVGREMODE1)    = 0x26;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4MCVXLANMODE0)    = 0x27;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4VXLANMODE1)      = 0x28;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6MCVXLANMODE0)    = 0x29;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6MCVXLANMODE1)    = 0x2a;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4MCNVGREMODE0)    = 0x2b;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4NVGREMODE1)      = 0x2c;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6MCNVGREMODE0)    = 0x2d;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6MCNVGREMODE1)    = 0x2e;
    /*Duet2 USERIDHASHTYPE_TUNNELIPV4DA)              = 0x33;*/
    /*Duet2 USERIDHASHTYPE_SCLFLOWL2)                 = 0x35;*/
    /*DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4CAPWAP)          = 0x2f;*/
    /*DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6CAPWAP)          = 0x30;*/
    /*DRV_CONST(DRV_USERIDHASHTYPE_TUNNELCAPWAPRMAC)          = 0x31;*/
    /*DRV_CONST(DRV_USERIDHASHTYPE_TUNNELCAPWAPRMACRID)       = 0x32;*/
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELMPLS)                = 0x34;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6)                = 0x33;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6GREKEY)          = 0x34;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6UDP)             = 0x35;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6DA)              = 0x36;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4DA)              = 0x37;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV4CLOUDSEC)        = 0x38;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6CLOUDSEC)        = 0x39;
    DRV_CONST(DRV_USERIDHASHTYPE_TUNNELTYPE_END)        = DRV_CONST(DRV_USERIDHASHTYPE_TUNNELIPV6CLOUDSEC);
    DRV_CONST(DRV_USERIDHASHTYPE_SCLFLOWL2)                 = 0x3a;
    DRV_CONST(DRV_USERIDHASHTYPE_SCLFLOWL2UDF)              = 0x3b;
    DRV_CONST(DRV_USERIDHASHTYPE_SCLFLOWL3UDF)              = 0x3c;
    DRV_CONST(DRV_USERIDHASHTYPE_SCLFLOWTYPE_END)        = DRV_CONST(DRV_USERIDHASHTYPE_SCLFLOWL3UDF);
    DRV_CONST(DRV_USERIDPORTHASHTYPE_DISABLE)               = 0x0;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_DOUBLEVLANPORT)        = 0x1;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_SVLANPORT)             = 0x2;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_CVLANPORT)             = 0x3;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_SVLANCOSPORT)          = 0x4;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_CVLANCOSPORT)          = 0x5;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_MACPORT)               = 0x6;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_IPSAPORT)              = 0x7;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_MAC)                   = 0x8;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_IPSA)                  = 0x9;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_PORT)                  = 0xa;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_SVLANMACSA)            = 0xb;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_SVLAN)                 = 0xc;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_ECIDNAMESPACE)         = 0xd;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_INGECIDNAMESPACE)      = 0xe;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_IPDA)                  = 0x11;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_SVLANDSCPPORT)         = 0x13;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_SCLTYPE_END)         = DRV_CONST(DRV_USERIDPORTHASHTYPE_SVLANDSCPPORT) ;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_TUNNEL)                = 0x1d;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_SCLFLOW)               = 0x1e;
    DRV_CONST(DRV_USERIDPORTHASHTYPE_TRILL)                 = 0x1f;

    DRV_CONST(DRV_UDFPOSTYPE_RSV)                     = 0x7;

    DRV_CONST(DRV_STK_MUX_TYPE_HDR_REGULAR_PORT)      = 0x0;
    DRV_CONST(DRV_STK_MUX_TYPE_HDR_WITHOUT_TUNNEL)    = 0x7;
    DRV_CONST(DRV_STK_MUX_TYPE_HDR_WITH_L2)           = 0x8;
    DRV_CONST(DRV_STK_MUX_TYPE_HDR_WITH_L2_AND_IPV4)  = 0xF;
    DRV_CONST(DRV_STK_MUX_TYPE_HDR_WITH_L2_AND_IPV6)  = 0xF;
    DRV_CONST(DRV_STK_MUX_TYPE_HDR_WITH_IPV4)         = 0xF;
    DRV_CONST(DRV_STK_MUX_TYPE_HDR_WITH_IPV6)         = 0xF;

    DRV_CONST(DRV_DMA_PACKET_TX_CHAN_NUM) = 4;
    DRV_CONST(DRV_DMA_PACKET_RX_CHAN_NUM) = 8;
    DRV_CONST(DRV_DMA_PACKET_RX0_CHAN_ID) = 0;
    DRV_CONST(DRV_DMA_PACKET_RX1_CHAN_ID) = 1;
    DRV_CONST(DRV_DMA_PACKET_RX2_CHAN_ID) = 2;
    DRV_CONST(DRV_DMA_PACKET_RX3_CHAN_ID) = 3;
    DRV_CONST(DRV_DMA_PACKET_RX4_CHAN_ID) = 4;
    DRV_CONST(DRV_DMA_PACKET_RX5_CHAN_ID) = 5;
    DRV_CONST(DRV_DMA_PACKET_RX6_CHAN_ID) = 6;
    DRV_CONST(DRV_DMA_PACKET_RX7_CHAN_ID) = 7;
    DRV_CONST(DRV_DMA_PACKET_TX0_CHAN_ID) = 8;
    DRV_CONST(DRV_DMA_PACKET_TX1_CHAN_ID) = 9;
    DRV_CONST(DRV_DMA_PACKET_TX2_CHAN_ID) = 10;
    DRV_CONST(DRV_DMA_PACKET_TX3_CHAN_ID) = 11;
    DRV_CONST(DRV_DMA_TBL_RD_CHAN_ID)     = 12;
    DRV_CONST(DRV_DMA_PORT_STATS_CHAN_ID) = 13;
    DRV_CONST(DRV_DMA_FLOW_STATS_CHAN_ID) = 14;
    DRV_CONST(DRV_DMA_BUF_SCAN_CHAN_ID)   = 0xFF;
    DRV_CONST(DRV_DMA_REG_MAX_CHAN_ID)    = 15;
    DRV_CONST(DRV_DMA_TBL_RD1_CHAN_ID)    = 16;
    DRV_CONST(DRV_DMA_TBL_RD2_CHAN_ID)    = 17;
    DRV_CONST(DRV_DMA_TBL_WR_CHAN_ID)     = 18;
    DRV_CONST(DRV_DMA_TBL_WR1_CHAN_ID)    = 19;
    DRV_CONST(DRV_DMA_LEARNING_CHAN_ID)   = 20;
    DRV_CONST(DRV_DMA_HASHKEY_CHAN_ID)    = 21;
    DRV_CONST(DRV_DMA_IPFIX_CHAN_ID)      = 22;
    DRV_CONST(DRV_DMA_BUFFER_CHAN_ID)     = 23;
    DRV_CONST(DRV_DMA_LATENCY_CHAN_ID)    = 24;
    DRV_CONST(DRV_DMA_EFD_CHAN_ID)        = 25;
    DRV_CONST(DRV_DMA_OAM_CHAN_ID)        = 26;
    DRV_CONST(DRV_DMA_SC_OAM_CHAN_ID)     = 27;
    DRV_CONST(DRV_DMA_TCAM_SCAN_CHAN_ID)  = 28;
    /* Unused for TsingMa.MX start */
    DRV_CONST(DRV_DMA_SDC_CHAN_ID)        = 0xFFFFFFFF;
    DRV_CONST(DRV_DMA_MONITOR_CHAN_ID)    = 0xFFFFFFFF;
    /* Unused for TsingMa.MX end */
    DRV_CONST(DRV_DMA_PKT_TX_TIMER_CHAN_ID) = 11;

    DRV_CONST(DRV_DMA_TCAM_SCAN_DESC_NUM) = 36;
    DRV_CONST(DRV_DMA_MAX_CHAN_ID)        = 20;

    DRV_CONST(DRV_FLOWPORTTYPE_BITMAP)                      = 0x0;
    DRV_CONST(DRV_FLOWPORTTYPE_GPORT)                       = 0x1;
    DRV_CONST(DRV_FLOWPORTTYPE_LPORT)                       = 0x2;
    DRV_CONST(DRV_FLOWPORTTYPE_METADATA)                    = 0x3;

    DRV_CONST(DRV_FIBNATPBRTCAMKEYTYPE_IPV4PBR)             = 0x0;
    DRV_CONST(DRV_FIBNATPBRTCAMKEYTYPE_IPV6PBR)             = 0x1;
    DRV_CONST(DRV_FIBNATPBRTCAMKEYTYPE_IPV4NAT)             = 0x2;
    DRV_CONST(DRV_FIBNATPBRTCAMKEYTYPE_IPV6NAT)             = 0x3;

    DRV_CONST(DRV_UDFTYPE_L2UDF)                            = 0x0;
    DRV_CONST(DRV_UDFTYPE_L3UDF)                            = 0x1;
    DRV_CONST(DRV_UDFTYPE_L4UDF)                            = 0x2;
    DRV_CONST(DRV_UDFTYPE_METADATA)                         = 0x3;

    DRV_CONST(DRV_VLANIDACTIONTYPE_NONE)                    = 0x0;
    DRV_CONST(DRV_VLANIDACTIONTYPE_SWAP)                    = 0x1;
    DRV_CONST(DRV_VLANIDACTIONTYPE_USER)                    = 0x2;

    DRV_CONST(DRV_VTAGACTIONTYPE_NONE)                      = 0x0;
    DRV_CONST(DRV_VTAGACTIONTYPE_MODIFY)                    = 0x3;
    DRV_CONST(DRV_VTAGACTIONTYPE_ADD)                       = 0x1;
    DRV_CONST(DRV_VTAGACTIONTYPE_DELETE)                    = 0x2;

    DRV_CONST(DRV_GEMHASHTYPE_PORT)                         = 0x1;

    DRV_CONST(DRV_IPFIXHASHTYPE_INVALID)                    = 0x0;
    DRV_CONST(DRV_IPFIXHASHTYPE_L2)                         = 0x1;
    DRV_CONST(DRV_IPFIXHASHTYPE_L2L3)                       = 0x2;
    DRV_CONST(DRV_IPFIXHASHTYPE_L3IPV4)                     = 0x3;
    DRV_CONST(DRV_IPFIXHASHTYPE_L3IPV6)                     = 0x4;
    DRV_CONST(DRV_IPFIXHASHTYPE_L3MPLS)                     = 0x5;

    DRV_CONST(DRV_MPLSHASHTYPE_LABEL)                       = 0x0;

    DRV_CONST(DRV_OAMHASHTYPE_ETH)                          = 0x0;
    DRV_CONST(DRV_OAMHASHTYPE_BFD)                          = 0x1;
    DRV_CONST(DRV_OAMHASHTYPE_MPLSLABEL)                    = 0x2;
    DRV_CONST(DRV_OAMHASHTYPE_MPLSSECTION)                  = 0x3;
    DRV_CONST(DRV_OAMHASHTYPE_RMEP)                         = 0x4;

    DRV_CONST(DRV_FIBHOST0HASHTYPE_FCOE)                    = 0x0;
    DRV_CONST(DRV_FIBHOST0HASHTYPE_IPV4)                    = 0x1;
    DRV_CONST(DRV_FIBHOST0HASHTYPE_IPV6MCAST)               = 0x2;
    DRV_CONST(DRV_FIBHOST0HASHTYPE_IPV6UCAST)               = 0x3;
    DRV_CONST(DRV_FIBHOST0HASHTYPE_MAC)                     = 0x4;
    DRV_CONST(DRV_FIBHOST0HASHTYPE_MACIPV6MCAST)            = 0x5;
    DRV_CONST(DRV_FIBHOST0HASHTYPE_TRILL)                   = 0x6;

    DRV_CONST(DRV_FIBHOST1HASHTYPE_FCOERPF)                 = 0x0;
    DRV_CONST(DRV_FIBHOST1HASHTYPE_IPV4MCAST)               = 0x1;
    DRV_CONST(DRV_FIBHOST1HASHTYPE_IPV4NATDAPORT)           = 0x2;
    DRV_CONST(DRV_FIBHOST1HASHTYPE_IPV4NATSAPORT)           = 0x3;
    DRV_CONST(DRV_FIBHOST1HASHTYPE_IPV6MCAST)               = 0x4;
    DRV_CONST(DRV_FIBHOST1HASHTYPE_IPV6NATDAPORT)           = 0x5;
    DRV_CONST(DRV_FIBHOST1HASHTYPE_IPV6NATSAPORT)           = 0x6;
    DRV_CONST(DRV_FIBHOST1HASHTYPE_MACIPV4MCAST)            = 0x7;
    DRV_CONST(DRV_FIBHOST1HASHTYPE_MACIPV6MCAST)            = 0x8;
    DRV_CONST(DRV_FIBHOST1HASHTYPE_TRILLMCASTVLAN)          = 0x9;
    DRV_CONST(DRV_FIB_HOST0_CAM_NUM)        = 32;
    DRV_CONST(DRV_FIB_HOST1_CAM_NUM)        = 32;
    DRV_CONST(DRV_FLOW_HASH_CAM_NUM)        = 32;
    DRV_CONST(DRV_USER_ID_HASH_CAM_NUM)     = 0;
    DRV_CONST(DRV_MPLS_HASH_CAM_NUM)        = 64;
    DRV_CONST(DRV_OAM_HASH_CAM_NUM)         = 64;
    DRV_CONST(DRV_RMEP_HASH_CAM_NUM)        = 32;
    DRV_CONST(DRV_GEM_PORT_HASH_CAM_NUM)    = 32;
    DRV_CONST(DRV_L2EDITTYPE_NONE)          = 0x0;
    DRV_CONST(DRV_L2EDITTYPE_ADDETH1X)      = 0x1;
    DRV_CONST(DRV_L2EDITTYPE_ADDETH2X)      = 0x2;
    DRV_CONST(DRV_L2EDITTYPE_ADDRAW)        = 0x3;
    DRV_CONST(DRV_L2EDITTYPE_AUTOETH1X)     = 0x4;
    DRV_CONST(DRV_L2EDITTYPE_AUTOETH2X)     = 0x5;
    DRV_CONST(DRV_L2EDITTYPE_RWETH1X)       = 0x9;
    DRV_CONST(DRV_L2EDITTYPE_RWETH2X)       = 0xa;
    DRV_CONST(DRV_L2EDITTYPE_AUTOETH1X)     = 0x4;
    DRV_CONST(DRV_L2EDITTYPE_AUTOETH2X)     = 0x5;
    DRV_CONST(DRV_L2EDITTYPE_GEMPORT)       = 0xe;
    DRV_CONST(DRV_L2EDITTYPE_LOOPBACK)      = 0xf;
    DRV_CONST(DRV_L3EDITTYPE_NONE)          = 0x0;
    DRV_CONST(DRV_L3EDITTYPE_ADDIP4)        = 0x1;
    DRV_CONST(DRV_L3EDITTYPE_ADDIP44X)      = 0x2;
    DRV_CONST(DRV_L3EDITTYPE_ADDIP6)        = 0x3;
    DRV_CONST(DRV_L3EDITTYPE_MPLS1X)        = 0x4;
    DRV_CONST(DRV_L3EDITTYPE_MPLS2X)        = 0x5;
    DRV_CONST(DRV_L3EDITTYPE_MPLS4X)        = 0x6;
    DRV_CONST(DRV_L3EDITTYPE_ADDRAW)        = 0x7;
    DRV_CONST(DRV_L3EDITTYPE_RWIP41X)       = 0x8;
    DRV_CONST(DRV_L3EDITTYPE_RWIP4)         = 0x9;
    DRV_CONST(DRV_L3EDITTYPE_RWIP6)         = 0xa;
    DRV_CONST(DRV_L3EDITTYPE_RWFLEX)        = 0xb;
    DRV_CONST(DRV_L3EDITTYPE_INSFLEX)       = 0xc;
    DRV_CONST(DRV_L3EDITTYPE_DELMPLS)       = 0xd;
    DRV_CONST(DRV_L3EDITTYPE_DELFLEX)       = 0xe;
    DRV_CONST(DRV_L3EDITTYPE_LOOPBACK)      = 0xf;
    DRV_CONST(DRV_L3EDITTYPE_ADDTRILL)      = 0x10;
    DRV_CONST(DRV_L3EDITTYPE_RWIP68X)       = 0x11;
    DRV_CONST(DRV_L3EDITTYPE_ADDIP68X)      = 0x12;

    DRV_CONST(DRV_NALPM_SRAM_TYPE_V4_32)    = 0x1;
    DRV_CONST(DRV_NALPM_SRAM_TYPE_V6_64)    = 0x2;
    DRV_CONST(DRV_NALPM_SRAM_TYPE_V6_128)   = 0x3;

    DRV_CONST(DRV_MAX_LPM_TCAM_NUM)         = 6;
    DRV_CONST(DRV_MAX_NOR_TCAM_NUM)         = 26;
    DRV_CONST(DRV_EPE_DISCARD_TYPE_NUM)     = 62;

    DRV_CONST(DRV_PARSER_L4_TYPE_UDP)       = 3;
    DRV_CONST(DRV_PARSER_L4_TYPE_GRE)       = 2;
    DRV_CONST(DRV_PARSER_L4_TYPE_TCP)       = 1;
    DRV_CONST(DRV_PARSER_L4_USER_TYPE_UDP_VXLAN)    = 8;
    DRV_CONST(DRV_KEY_METADATA_BITS)                        = 15;

    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_INVALIDPDU)            = 0x0;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_SETCSLPI)              = 0x1;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_CLEARCSLPI)            = 0x2;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_SETCSLF)               = 0x3;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_CLEARCSLF)             = 0x4;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_SETCSRF)               = 0x5;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_CLEARCSRF)             = 0x6;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_SETDEXC)               = 0x7;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_CLEARDEXC)             = 0x8;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_SETDDEG)               = 0x9;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_CLEARDDEG)             = 0xa;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_APSTRIGGER)            = 0xb;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_SEQCHECKFAIL)          = 0xc;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_SAPICHECKFAIL)         = 0xd;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_SAPICHECKCLEAR)        = 0xe;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_DAPICHECKFAIL)         = 0xf;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_DAPICHECKCLEAR)        = 0x10;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_CSTYPEFAIL)            = 0x11;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_CSTYPEFAILCLEAR)       = 0x12;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_CRCERROR)              = 0x13;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_APSRX)                 = 0x14;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_OTHERPDU)              = 0x15;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_BASPERIODCHKFAIL)      = 0x16;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_PDUPROCINCPU)          = 0x17;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_SETRDI)                = 0x18;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_CLEARRDI)              = 0x19;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_FIRSTRXBLOCK)          = 0x1a;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_SETDREIEXC)            = 0x1b;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_CLEARDREIEXC)          = 0x1c;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_SETDREIDEG)            = 0x1d;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_CLEARDREIDEG)          = 0x1e;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_DLOCRXCLEAR)           = 0x1f;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_BASPERIODCHKCLEAR)     = 0x20;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_BASSEQMISMATCHCLEAR)   = 0x21;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_CVSEQMISMATCHCLEAR)    = 0x22;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_CSSEQMISMATCHCLEAR)    = 0x23;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_APSSEQMISMATCHCLEAR)   = 0x24;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE__1DMSEQMISMATCHCLEAR)  = 0x25;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_DMMSEQMISMATCHCLEAR)   = 0x26;
    DRV_CONST(DRV_FLEXEOAMDEFECTTYPE_DMRSEQMISMATCHCLEAR)   = 0x27;

    DRV_CONST(DRV_FLEXEOAMUPDATEDEFECTTYPE_INVALID)      = 0x0;
    DRV_CONST(DRV_FLEXEOAMUPDATEDEFECTTYPE_BASLOC)       = 0x1;
    DRV_CONST(DRV_FLEXEOAMUPDATEDEFECTTYPE_SIGNALFAIL)   = 0x2;
    DRV_CONST(DRV_FLEXEOAMUPDATEDEFECTTYPE_SIGNALOK)     = 0x3;
    DRV_CONST(DRV_FLEXEOAMUPDATEDEFECTTYPE_DLOCRXCLEAR)  = 0x4;

    DRV_CONST(DRV_EGRACL_L3K160_SHAREFIELDS_L4PORT_RNG_BMP) = 3;
    DRV_CONST(DRV_EGRACL_L3K160_SHAREFIELDS_DEFAULT)        = 0;

    DRV_CONST(DRV_DIAG_MAC_HASH_WIDTH)      = 87;
    DRV_CONST(DRV_DIAG_IPV4_HASH_WIDTH)     = 87;
    DRV_CONST(DRV_DIAG_MPLS_HASH_WIDTH)     = 35;
    DRV_CONST(DRV_DIAG_OAM_MEP_WIDTH)       = 180;
    DRV_CONST(DRV_DIAG_APS_WIDTH)           = 160;
    DRV_CONST(DRV_DIAG_FLEX_TCAM_WIDTH)     = 160;
    DRV_CONST(DRV_DIAG_EDIT_WIDTH)          = 100;

    DRV_CONST(DRV_ACCREQ_ADDR_HOST0) = 0x4c410ee4;
    DRV_CONST(DRV_ACCREQ_BITOFFSET_HOST0) = 17;
    DRV_CONST(DRV_ACCREQ_ADDR_FIB) = 0x4c422af0;
    DRV_CONST(DRV_ACCREQ_BITOFFSET_FIB) = 8;
    DRV_CONST(DRV_ACCREQ_ADDR_USERID) = 0x548d9f30;
    DRV_CONST(DRV_ACCREQ_BITOFFSET_USERID) = 3;
    DRV_CONST(DRV_ACCREQ_ADDR_CIDPAIR) = 0x54523d44;
    DRV_CONST(DRV_ACCREQ_BITOFFSET_CIDPAIRHASH) = 3;
    DRV_CONST(DRV_ACCREQ_ADDR_MPLS) = 0x4600ae7c;
    DRV_CONST(DRV_ACCREQ_BITOFFSET_MPLS) = 3;
    DRV_CONST(DRV_ACCREQ_ADDR_GEMPORT) = 0x4600b5d8;
    DRV_CONST(DRV_ACCREQ_BITOFFSET_GEMPORT) = 22;
    DRV_CONST(DRV_ACCREQ_ADDR_EGRESSSCL) = 0x460072dc;
    DRV_CONST(DRV_ACCREQ_BITOFFSET_EGRESSSCL) = 0;
    DRV_CONST(DRV_ACCREQ_ADDR_OAM) = 0x549a0a4c;
    DRV_CONST(DRV_ACCREQ_BITOFFSET_OAM) = 0;
    DRV_CONST(DRV_ACCREQ_ADDR_OAMRMEP) = 0x554687cc;
    DRV_CONST(DRV_ACCREQ_BITOFFSET_OAMRMEP) = 0;
    DRV_CONST(DRV_ACCREQ_ADDR_QUEUEHASH) = 0x80e4e8dc;
    DRV_CONST(DRV_ACCREQ_BITOFFSET_QUEUEHASH) = 16;

    DRV_CONST(DRV_OAM_MEPTYPE_ETH_CCM_MEP)       =0x0;
    DRV_CONST(DRV_OAM_MEPTYPE_PBT_CCM_MEP)       =0x1;
    DRV_CONST(DRV_OAM_MEPTYPE_TRILL_BFD_MEP)     =0x2;
    DRV_CONST(DRV_OAM_MEPTYPE_FFD_MEP)           =0x3;
    DRV_CONST(DRV_OAM_MEPTYPE_CV1_MEP)           =0x4;
    DRV_CONST(DRV_OAM_MEPTYPE_BFD_MEP)           =0x5;
    DRV_CONST(DRV_OAM_MEPTYPE_ACH_Y1731_MEP)     =0x6;
    DRV_CONST(DRV_OAM_MEPTYPE_ACH_BFD_MEP)       =0x7;
    DRV_CONST(DRV_OAM_MEPTYPE_EXT_ETH_CCM_MEP)   =0x8;
    DRV_CONST(DRV_OAM_MEPTYPE_TWAMP_MEP)         =0x9;
    DRV_CONST(DRV_OAM_MEPTYPE_EXT_ACH_Y1731_MEP) =0xa;

    DRV_CONST(DRV_DsDesc_done_f_START_WORD) = 0;
    DRV_CONST(DRV_DsDesc_done_f_START_BIT) = 16;
    DRV_CONST(DRV_DsDesc_done_f_BIT_WIDTH) = 1;
    DRV_CONST(DRV_DsDesc_u1_pkt_sop_f_START_WORD) = 0;
    DRV_CONST(DRV_DsDesc_u1_pkt_sop_f_START_BIT) = 0;
    DRV_CONST(DRV_DsDesc_u1_pkt_sop_f_BIT_WIDTH) = 1;
    DRV_CONST(DRV_DsDesc_u1_pkt_eop_f_START_WORD) = 0;
    DRV_CONST(DRV_DsDesc_u1_pkt_eop_f_START_BIT) = 1;
    DRV_CONST(DRV_DsDesc_u1_pkt_eop_f_BIT_WIDTH) = 1;
    DRV_CONST(DRV_DsDesc_memAddr_f_START_WORD) = 2;
    DRV_CONST(DRV_DsDesc_memAddr_f_START_BIT) = 4;
    DRV_CONST(DRV_DsDesc_memAddr_f_BIT_WIDTH) = 28;
    DRV_CONST(DRV_DsDesc_realSize_f_START_WORD) = 1;
    DRV_CONST(DRV_DsDesc_realSize_f_START_BIT) = 8;
    DRV_CONST(DRV_DsDesc_realSize_f_BIT_WIDTH) = 20;
    DRV_CONST(DRV_DsDesc_dataStruct_f_START_WORD) = 0;
    DRV_CONST(DRV_DsDesc_dataStruct_f_START_BIT) = 8;
    DRV_CONST(DRV_DsDesc_dataStruct_f_BIT_WIDTH) = 6;
    DRV_CONST(DRV_DsDesc_error_f_START_WORD) = 0;
    DRV_CONST(DRV_DsDesc_error_f_START_BIT) = 17;
    DRV_CONST(DRV_DsDesc_error_f_BIT_WIDTH) = 1;
    DRV_CONST(DRV_DsDesc_pause_f_START_WORD) = 0;
    DRV_CONST(DRV_DsDesc_pause_f_START_BIT) = 15;
    DRV_CONST(DRV_DsDesc_pause_f_BIT_WIDTH) = 1;
    DRV_CONST(DRV_DsDesc_cfgSize_f_START_WORD) = 0;
    DRV_CONST(DRV_DsDesc_cfgSize_f_START_BIT) = 20;
    DRV_CONST(DRV_DsDesc_cfgSize_f_BIT_WIDTH) = 12;
    DRV_CONST(DRV_DsDesc_cfgSize2_f_START_WORD) = 1;
    DRV_CONST(DRV_DsDesc_cfgSize2_f_START_BIT) = 0;
    DRV_CONST(DRV_DsDesc_cfgSize2_f_BIT_WIDTH) = 8;
    DRV_CONST(DRV_DsDesc_valid_f_START_WORD) = 7;
    DRV_CONST(DRV_DsDesc_valid_f_START_BIT) = 31;
    DRV_CONST(DRV_DsDesc_valid_f_BIT_WIDTH) = 1;
    DRV_CONST(DRV_DsDesc_tsAddr_f_START_WORD) = 3;
    DRV_CONST(DRV_DsDesc_tsAddr_f_START_BIT) = 0;
    DRV_CONST(DRV_DsDesc_tsAddr_f_BIT_WIDTH) = 32;

    DRV_CONST(DRV_HOST0_SINGLE_KEY_BYTE) = 12;
    DRV_CONST(DRV_HOST0_DOUBLE_KEY_BYTE) = 24;
    DRV_CONST(DRV_HOST0_QUAD_KEY_BYTE)   = 48;
    DRV_CONST(DRV_NAT_TCAM_AGING_BASE) = 16384;

    DRV_CONST(DRV_MIRROR_INGRESS_L2SPAN_DISCARD) = 0x1;
    DRV_CONST(DRV_MIRROR_INGRESS_L3SPAN_DISCARD) = 0x2;
    DRV_CONST(DRV_MIRROR_INGRESS_ACLLOG_PRI_DISCARD) = 0x3FC;
    DRV_CONST(DRV_MIRROR_INGRESS_IPFIX_MIRROR_DISCARD) = 0x800;
    DRV_CONST(DRV_MIRROR_EGRESS_L2SPAN_DISCARD) = 0x1;
    DRV_CONST(DRV_MIRROR_EGRESS_L3SPAN_DISCARD) = 0x2;
    DRV_CONST(DRV_MIRROR_EGRESS_ACLLOG_PRI_DISCARD) = 0x1C;
    DRV_CONST(DRV_MIRROR_EGRESS_IPFIX_MIRROR_DISCARD) = 0x40;
    return 0;
}

extern int32
drv_tmm_ftm_api_init(uint8 lchip);
extern int32
drv_tmm_ser_api_init(uint8 lchip);
int32
drv_tmm_chip_read_hss15g(uint8 lchip, uint8 hss_id, uint32 addr, uint16* p_data)
{
    return DRV_E_NONE;
}

/**
 @brief access hss15g control register
*/
int32
drv_tmm_chip_write_hss15g(uint8 lchip, uint8 hss_id, uint32 addr, uint16 data)
{
    return DRV_E_NONE;
}

uint8  hss_idx_shift[13] ={0,0,1,1,0,1,2,2,3,3,2,3,0};
uint8  hss_tbl_idx[13] =  {0,1,0,1,2,2,0,1,0,1,2,2,3};
uint32 cfg_tbl_list[4] = {HssOctal0RegAccCfg_t, HssOctal1RegAccCfg_t, HssOctalRegAccCfg_t, CpuMacHssQuadRegAccCfg_t};
uint32 rslt_tbl_list[4] = {HssOctal0RegAccResult_t, HssOctal1RegAccResult_t, HssOctalRegAccResult_t, CpuMacHssQuadRegAccResult_t};

extern int32 drv_usw_chip_sram_tbl_read2(uint8 lchip, uint32 index, uint32 cmd, uint8 oper_bmp, uint32* data);
extern int32 drv_usw_chip_sram_tbl_write2(uint8 lchip, uint32 index, uint32 cmd, uint8 oper_bmp, uint32* data);

/**
 @brief access hss28g control register
*/
int32
drv_tmm_chip_read_hss28g(uint8 lchip, uint8 hss_id, uint32 addr, uint16* p_data)
{
#ifdef EMULATION_ENV
#else
    int32  ret        = 0;
    uint8  tbl_idx    = hss_tbl_idx[hss_id];
    uint32 index      = hss_idx_shift[hss_id] << 24;
    uint32 timeout    = 0x6400;
    HssOctal0RegAccCfg_m acc_cfg;
    HssOctal0RegAccResult_m acc_rst;

    DRV_INIT_CHECK(lchip);

    /*1. Clear  HssOctal0RegAccResult*/
    sal_memset(&acc_rst, 0, sizeof(HssOctal0RegAccResult_m));
    drv_usw_chip_sram_tbl_write2(lchip, index, DRV_IOW(rslt_tbl_list[tbl_idx], DRV_ENTRY_FLAG), 0, (uint32*)&acc_rst);

    /*2. write HssOctal0RegAccCfg to run read action*/
    SetHssOctal0RegAccCfg(V, hssAcc0Addr_f,    &acc_cfg, (addr & 0xffff));
    SetHssOctal0RegAccCfg(V, hssAcc0Id_f,      &acc_cfg, ((addr >> 16) & 0xff));
    SetHssOctal0RegAccCfg(V, hssAcc0IsBcast_f, &acc_cfg, 0);
    SetHssOctal0RegAccCfg(V, hssAcc0IsRead_f,  &acc_cfg, 1);
    SetHssOctal0RegAccCfg(V, hssAcc0Valid_f,   &acc_cfg, 1);
    SetHssOctal0RegAccCfg(V, hssAcc0Wdata_f,   &acc_cfg, 0);
    ret = drv_usw_chip_sram_tbl_write2(lchip, index, DRV_IOW(cfg_tbl_list[tbl_idx], DRV_ENTRY_FLAG), 0, (uint32*)&acc_cfg);
    if (ret < 0)
    {
        return DRV_E_ACCESS_HSS12G_FAIL;
    }

    /*3. read HssOctal0RegAccResult to get return value*/
    do{
        drv_usw_chip_sram_tbl_read2(lchip, index, DRV_IOR(rslt_tbl_list[tbl_idx], DRV_ENTRY_FLAG), 0, (uint32*)&acc_rst);
        if(GetHssOctal0RegAccResult(V, hssAcc0Ack_f, &acc_rst))
        {
            if(GetHssOctal0RegAccResult(V, hssAcc0AckError_f, &acc_rst))
            {
                return DRV_E_DATAPATH_READ_CHIP_FAIL;
            }
            break;
        }
    }while (--timeout);

    if(0 == timeout)
    {
        return DRV_E_TIME_OUT;
    }
    *p_data = GetHssOctal0RegAccResult(V,hssAcc0AckData_f,&acc_rst);
#endif
    return DRV_E_NONE;
}


/**
 @brief access hss28g control register
*/
int32
drv_tmm_chip_write_hss28g(uint8 lchip, uint8 hss_id, uint32 addr, uint16 data)
{
#ifdef EMULATION_ENV
#else
    int32  ret     = 0;
    uint32 index   = hss_idx_shift[hss_id] << 24;
    uint8  tbl_idx = hss_tbl_idx[hss_id];
    HssOctal0RegAccCfg_m acc_cfg;

    DRV_INIT_CHECK(lchip);

    /* 1. write HssOctal0RegAccCfg to run write action */
    SetHssOctal0RegAccCfg(V, hssAcc0Addr_f,    &acc_cfg, (addr & 0xffff));
    SetHssOctal0RegAccCfg(V, hssAcc0Wdata_f,   &acc_cfg, data);
    SetHssOctal0RegAccCfg(V, hssAcc0Id_f,      &acc_cfg, ((addr >> 16) & 0xff));
    SetHssOctal0RegAccCfg(V, hssAcc0IsBcast_f, &acc_cfg, ((addr >> 24) & 0xff));
    SetHssOctal0RegAccCfg(V, hssAcc0IsRead_f,  &acc_cfg, 0);
    SetHssOctal0RegAccCfg(V, hssAcc0Valid_f,   &acc_cfg, 1);
    ret = drv_usw_chip_sram_tbl_write2(lchip, index, DRV_IOW(cfg_tbl_list[tbl_idx], DRV_ENTRY_FLAG), 0, (uint32*)&acc_cfg);
    if (ret < 0)
    {
        return DRV_E_ACCESS_HSS12G_FAIL;
    }
#endif

    return DRV_E_NONE;
}


drv_io_tcam_db_t drv_tmm_io_tcam_db[DRV_IO_TCAM_TYPE_NUM] = {
/*FLOW*/  {0,     0,                              0,                              0, 0, 0},
/*LPM*/   {14,    DRV_LPM_KEY_BYTES_PER_ENTRY,    LpmTcamTcamMem_t,               LpmTcamTcamMem_tcamEntryValid_f, 4, DRV_FTM_LPM_TCAM_KEY0},
/*NAT*/   {14,    DRV_LPM_KEY_BYTES_PER_ENTRY,    LpmTcamTcamMem_t,               LpmTcamTcamMem_tcamEntryValid_f, 4, DRV_FTM_LPM_TCAM_KEY4},
/*ACL0*/  {11,    DRV_BYTES_PER_ENTRY*2,          ProgramAclTcamMem_t,            ProgramAclTcamMem_valid_f, 16, DRV_FTM_TCAM_KEY4},
/*ACL1*/  {10,    DRV_BYTES_PER_ENTRY*2,          EgressAclTcamTcamMem_t,         EgressAclTcamTcamMem_tcamEntryValid_f, 16, DRV_FTM_TCAM_KEY20},
/*SCL0*/  {9,     DRV_BYTES_PER_ENTRY,            UserIdHashTcamMem_t,            UserIdHashTcamMem_tcamEntryValid_f, 8, DRV_FTM_TCAM_KEY0},
/*SCL1*/  {10,    DRV_BYTES_PER_ENTRY*2,          UserIdTcamMem_t,                UserIdTcamMem_tcamEntryValid_f, 16, DRV_FTM_TCAM_KEY2},
/*SCL2*/  {8,     DRV_BYTES_PER_ENTRY,            EgrSclHashTcamMem_t,            EgrSclHashTcamMem_tcamEntryValid_f, 8, DRV_FTM_TCAM_KEY24},
/*CID*/   {0,     8,                              IpeCidTcamMem_t,                IpeCidTcamMem_tcamEntryValid_f, 4, DRV_FTM_CID_TCAM},
/*QUE*/   {0,     0,                              0,                              0, 0, 0},
/*LTID*/  {0,     16,                             DsLtidSelectTcamMem_t,          DsLtidSelectTcamMem_valid_f, 16, DRV_FTM_SEL_TCAM},
/*VMAC*/  {0,     12,                             IpeHdrAdjRouterMacTcamMem_t,    IpeHdrAdjRouterMacTcamMem_tcamEntryValid_f, 8, DRV_FTM_RMAC_TCAM},
/*UDF*/   {0,     12,                             IpeHdrAdjUdfTcamMem_t,          IpeHdrAdjUdfTcamMem_tcamEntryValid_f, 8, DRV_FTM_UDF_TCAM},
};


/**
 @brief get flow tcam blknum and local index
*/
static  int32
drv_tmm_tcam_get_blknum_index(uint8 lchip, tbls_id_t tbl_id, uint32 index, uint32 *blknum, uint32 *local_idx)
{
    *local_idx = index;
    *blknum = TCAM_KEY_BLOCK_ID(lchip, tbl_id, 0);

    return DRV_E_NONE;
}

static drv_mchip_sdb_t drv_sdb_api =
{
    drv_sdb_store
};

int32
drv_tbls_list_init_tmm(uint8 lchip)
{
    uint8 i = 0;
    uint16 tbl_idx = 0;

    p_drv_master[lchip]->p_tbl_ext_info = (tables_ext_info_t*)mem_malloc(MEM_SYSTEM_MODULE, (MaxTblId_t+1)*sizeof(tables_ext_info_t));
    if(!p_drv_master[lchip]->p_tbl_ext_info)
    {
        return -1;
    }
    sal_memset(p_drv_master[lchip]->p_tbl_ext_info, 0, (MaxTblId_t+1)*sizeof(tables_ext_info_t));

    p_drv_master[lchip]->p_tbl_mapping = (uint16*)mem_malloc(MEM_SYSTEM_MODULE, MaxTblId_t*sizeof(uint16));
    if(!p_drv_master[lchip]->p_tbl_mapping)
    {
        return -1;
    }
    
    p_drv_master[lchip]->p_tbl_info = drv_tmm_tbls_list;
    for (tbl_idx = 0; tbl_idx < MaxTblId_t; tbl_idx++)
    {
        p_drv_master[lchip]->p_tbl_mapping[tbl_idx] = (sizeof(drv_tmm_tbls_list)/sizeof(tables_info_t) -1);
    }
    for (tbl_idx = 0; tbl_idx < ((sizeof(drv_tmm_tbls_list)/sizeof(tables_info_t)) - 1); tbl_idx++)
    {
        p_drv_master[lchip]->p_tbl_mapping[p_drv_master[lchip]->p_tbl_info[tbl_idx].tbl_id] = tbl_idx;
    }

    p_drv_master[lchip]->p_mem_info = drv_tmm_mem;
    p_drv_master[lchip]->drv_io_tcam_db = drv_tmm_io_tcam_db;

#ifndef DRV_DS_LITE
    p_drv_master[lchip]->p_tbl_name = drv_tmm_tbls_name_list;
#endif

    for (i = 0; i < DRV_IO_TCAM_TYPE_NUM; i++)
    {
        p_drv_master[lchip]->drv_io_tcam_db[i].drv_tcam_get_block_info = drv_tmm_tcam_get_blknum_index;

#if (1 == SDK_WORK_PLATFORM)
        p_drv_master[lchip]->drv_io_tcam_db[i].hw_words = drv_tmm_io_tcam_db[i].tcam_mem_tbl_id? TABLE_INFO(lchip, drv_tmm_io_tcam_db[i].tcam_mem_tbl_id).byte/4:0;
#endif
    }

    p_drv_master[lchip]->drv_ecc_data.p_intr_tbl = drv_ecc_tmm_err_intr_tbl;
    p_drv_master[lchip]->drv_ecc_data.p_sbe_cnt  = drv_ecc_tmm_sbe_cnt;
    p_drv_master[lchip]->drv_ecc_data.p_scan_tcam_tbl = drv_ecc_tmm_scan_tcam_tbl;

    drv_mem_init_tmm(lchip);

    p_drv_master[lchip]->p_enum_value = drv_tmm_enum;
    p_drv_master[lchip]->p_tcam_map = drv_tmm_tcam_mem_map;

    p_drv_master[lchip]->drv_chip_read_hss15g = drv_tmm_chip_read_hss15g;
    p_drv_master[lchip]->drv_chip_write_hss15g = drv_tmm_chip_write_hss15g;
    p_drv_master[lchip]->drv_chip_read_hss28g = drv_tmm_chip_read_hss28g;
    p_drv_master[lchip]->drv_chip_write_hss28g = drv_tmm_chip_write_hss28g;
    p_drv_master[lchip]->mchip_api.p_mchip_sdb = &drv_sdb_api;
    drv_enum_init_tmm(lchip);

    drv_tmm_ftm_api_init(lchip);

    drv_tmm_ser_api_init(lchip);

    return 0;
}


int32
drv_tbls_list_deinit_tmm(uint8 lchip)
{
    if(p_drv_master[lchip]->p_tbl_ext_info)
    {
        mem_free(p_drv_master[lchip]->p_tbl_ext_info);
    }
    if(p_drv_master[lchip]->p_tbl_mapping)
    {
        mem_free(p_drv_master[lchip]->p_tbl_mapping);
    }
    return 0;
}

#undef DRV_DEF_M
#undef DRV_DEF_D
#undef DRV_DEF_DD
#undef DRV_DEF_F
#undef DRV_DEF_FF
#undef DRV_DEF_C
#undef DRV_DEF_E




#endif




